s908gr16ag4cfj Freescale Semiconductor, Inc, s908gr16ag4cfj Datasheet - Page 186

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s908gr16ag4cfj

Manufacturer Part Number
s908gr16ag4cfj
Description
M68hc08 Microcontrollers Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
System Integration Module (SIM)
15.6.2 Stop Mode
In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a
module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery
time has elapsed. Reset causes an exit from stop mode.
The SIM disables the clock generator module outputs (CGMOUT and CGMXCLK) in stop mode, stopping
the CPU and peripherals. Stop recovery time is selectable using the SSREC bit in the CONFIG1 register.
If SSREC is set, stop recovery is reduced from the normal delay of 4096 CGMXCLK cycles down to 32.
This is ideal for applications using canned oscillators that do not require long startup times from stop
mode.
The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop
recovery. It is then used to time the recovery period.
Figure 15-19
186
shows stop mode recovery time from interrupt.
EXITSTOPWAIT
Note: EXITSTOPWAIT = RST pin or CPU interrupt
External crystal applications should use the full stop recovery time by
clearing the SSREC bit unless the OSCENINSTOP bit is set in CONFIG2.
To minimize stop current, all pins configured as inputs should be driven to
a 1 or 0.
CGMXCLK
RST
IDB
IAB
IDB
IAB
$A6
Figure 15-17. Wait Recovery from Internal Reset
$A6
Figure 15-16. Wait Recovery from Interrupt
$6E0B
$A6
$6E0B
$A6
MC68HC908GR16A Data Sheet, Rev. 1.0
$A6
$A6
CYCLES
$6E0C
32
NOTE
NOTE
$01
Figure 15-18
$00FF
CYCLES
32
$0B
$00FE
$6E
shows stop mode entry timing.
RST VCT H
$00FD
RST VCT L
$00FC
Freescale Semiconductor

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