s908gr16ag4cfj Freescale Semiconductor, Inc, s908gr16ag4cfj Datasheet - Page 55

• Manufacturer Part Number: s908gr16ag4cfj
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

3.8.3 ADC Clock Register
The ADC clock register (ADCLK) selects the clock frequency for the ADC.
ADIV2–ADIV0 — ADC Clock Prescaler Bits
ADICLK — ADC Input Clock Select Bit
MODE1 and MODE0 — Modes of Result Justification Bits
Freescale Semiconductor
ADIV2–ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate the internal
ADC clock.
approximately 1 MHz.
ADICLK selects either the bus clock or the oscillator output clock (CGMXCLK) as the input clock
source to generate the internal ADC clock. Reset selects CGMXCLK as the ADC clock source.
The ADC requires a clock rate of approximately 1 MHz for correct operation. If the selected clock
source is not fast enough, the ADC will generate incorrect conversions. See
Characteristics.
MODE1 and MODE0 select among four modes of operation. The manner in which the ADC conversion
results will be placed in the ADC data registers is controlled by these modes of operation. Reset returns
right-justified mode.
1 = Internal bus clock
0 = Oscillator output clock (CGMXCLK)
00 = 8-bit truncation mode
01 = Right justified mode
10 = Left justified mode
11 = Left justified signed data mode
Address:
Table 3-2
Reset:
Read:
Write:
ADIV2
$003F
Bit 7
1. X = Don’t care
R
0
shows the available clock configurations. The ADC clock should be set to
ADIV2
0
0
0
0
1
f
ADIC
Figure 3-9. ADC Clock Register (ADCLK)
= Reserved
ADIV1
=
6
0
Table 3-2. ADC Clock Divide Ratio
MC68HC908GR16A Data Sheet, Rev. 1.0
ADIV1
f
X
CGMXCLK
0
0
1
1
(1)
ADIV0
5
0
ADIV[2:0]
ADIV0
or bus frequency
X
0
1
0
1
(1)
ADICLK
4
0
ADC input clock ÷ 1
ADC input clock ÷ 2
ADC input clock ÷ 4
ADC input clock ÷ 8
ADC input clock ÷ 16
= Unimplemented
MODE1
3
0
ADC Clock Rate
≅ 1 MHz
MODE0
2
1
R
1
0
20.10 5.0-Volt ADC
Bit 0
0
0
I/O Registers
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