ics8430-111 Integrated Device Technology, ics8430-111 Datasheet - Page 12

• Manufacturer Part Number: ics8430-111
• Description: Programmable Low-jitter Lvpecl Or Lvcmos-input Lvpecl-output 2-output 700-mhz Clock Synthesizer
• Manufacturer: Integrated Device Technology

T
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, termi-
nating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
IDT
RTT =
ERMINATION FOR
ICS8430-111
700MHZ, LOW JITTER, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
™
/ ICS
((V
F
™
FOUT
OH
IGURE
3.3V LVPECL FREQUENCY SYNTHESIZER
+ V
OL
5A. LVPECL O
) / (V
1
3.3V LVPECL O
CC
Z
Z
– 2)) – 2
o
o
= 50Ω
= 50Ω
Z
o
50Ω
UTPUT
T
RTT
ERMINATION
UTPUTS
50Ω
V
CC
FIN
- 2V
12
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion. Figures 5A and 5B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT
F
IGURE
5B. LVPECL O
Z
Z
o
o
= 50Ω
= 50Ω
ICS8430DY-111 REV. F JANUARY 29, 2007
125Ω
84Ω
UTPUT
3.3V
125Ω
84Ω
T
ERMINATION
PRELIMINARY
FIN