ics8430-111 Integrated Device Technology, ics8430-111 Datasheet - Page 2

• Manufacturer Part Number: ics8430-111
• Description: Programmable Low-jitter Lvpecl Or Lvcmos-input Lvpecl-output 2-output 700-mhz Clock Synthesizer
• Manufacturer: Integrated Device Technology

IDT
F
The ICS8430-111 features a fully integrated PLL and there-
fore requires no external components for setting the loop
bandwidth. A differential clock input is used as the input to the
on-chip oscillator. The output of the oscillator is divided by 16
prior to the phase detector. A16MHz clock input provides a
1MHz reference frequency. The VCO of the PLL operates over
a range of 200 to 700MHz. The output of the M divider is also
applied to the phase detector.
The phase detector and the M divider force the VCO output
frequency to be 2M times the reference frequency by adjusting
the VCO control voltage. Note that for some values of M (either
too high or too low), the PLL will not achieve lock. The output
of the VCO is scaled by a divider prior to being sent to each of
the LVPECL output buffers. The divider provides a 50% output
duty cycle.
The programmable features of the ICS8430-111 support two
input modes to program the M divider and N output divider.
The two input operational modes are parallel and serial. Fig-
ure 1 shows the timing diagram for each mode. In parallel mode
the nP_LOAD input is LOW. The data on inputs M0 through
M8 and N0 through N1 is passed directly to the M divider and
N output divider. On the LOW-to-HIGH transition of the
nP_LOAD input, the data is latched and the M divider remains
loaded until the next LOW transition on nP_LOAD or until a
serial event occurs. The TEST output is Mode 000 (shift regis-
ter out) when operating in the parallel input mode. The rela-
tionship between the VCO frequency, the crystal frequency
and the M divider is defined as follows:
*NOTE:
M0:M8, N0:N1
UNCTIONAL
ICS8430-111
700MHZ, LOW JITTER, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
™
S_CLOCK
nP_LOAD
nP_LOAD
/ ICS
S_LOAD
S_LOAD
S_DATA
The NULL timing slot must be observed.
™
3.3V LVPECL FREQUENCY SYNTHESIZER
D
ESCRIPTION
t
S
F
t
H
IGURE
fVCO =
1. P
t
M, N
S
ARALLEL
fxtal x
16
t
H
Time
2M
P
S
& S
ARALLEL
ERIAL
ERIAL
2
L
OADING
L
The M value and the required values of M0 through M8 are
shown in Table 3B, Programmable VCO Frequency Function
Table. Valid M values for which the PLL will achieve lock are
defined as 125 ≤ M ≤ 350. The frequency out is defined as
follows:
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the shift
register are loaded into the M divider and N output divider when
S_LOAD transitions from LOW-to-HIGH. The M divide and N
output divide values are latched on the HIGH-to-LOW transi-
tion of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA
input is passed directly to the M divider and N output divider on
each rising edge of S_CLOCK. The serial mode can be used to
program the M and N bits and test bits T1 and T0. The internal
registers T0 and T1 determine the state of the TEST output as
follows:
L
OAD
OADING
O
T1
0
0
1
1
PERATIONS
T0
0
1
0
1
S_Data, Shift Register Input
fout = fVCO =
Output of M divider
ICS8430DY-111 REV. F JANUARY 29, 2007
TEST Output
N
CMOS Fout
LOW
fxtal x
16
2M
t
N
S
PRELIMINARY