ics9248-192 Integrated Device Technology, ics9248-192 Datasheet
ics9248-192
Related parts for ics9248-192
ics9248-192 Summary of contents
Page 1
... SDATA 48MHz 24_48MHz / 2 REF CPU CPUCLK0 Stop DIVDER PCI PCICLK (5:0) Stop DIVDER 6 Power Groups VDD_Core, GND_Core = PLL core VDDREF, GNDREF = REF, X1, X2 VDDPCI, GNDPCI = PCICLK (5:0) VDD48, GND48 = 48MHz (1:0) ICS9248-192 Pin Configuration 1 28 VDDREF REF CPU_STOP PD# VDDLCPU 5 24 GNDLCPU ...
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... ICS9248-192 Pin Descriptions Pin number Pin name 1 GNDREF PD# 12, 11, 10 PCICLK (5:0) 8 GNDPCI 9 VDDPCI Sel48_24# 15 24_48MHz 13 SDATA 14 SCLK CPU3.3-2.5# 16 48MHz 17 GND48 18 VDD48 19 SEL 66/60# 20 VDD_Core 21 GND_Core 22 PCI_Stop# 23 CPUCLK0 24 GNDLCPU 25 VDDLCPU 26 CPU_STOP# 27 REF 28 VDDREF 0540F—10/27/05 Type Power Ground for 14.318 MHz reference clock outputs Input 14 ...
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... PD# pin will not cause clocks of a short or longer pulse than that of the running clock. The first clock pulse coming out of a stopped clock condition may be slightly distorted due to clock network charging circuitry. Board routing and signal loading may have a large impact on the initial clock distortion also. ICS9248-192 Power Management Requirements ...
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... ICS9248-192 General I The information in this section assumes familiarity with I How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D2 • ICS clock will acknowledge • Controller (host) sends a dummy command code • ICS clock will acknowledge • ...
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... ICS9248-192 PWD 00000 ...
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... ICS9248-192 Byte 1: PCI Stop ...
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... PD# and PCI_STOP# are shown in a high (true) state. PCI_STOP# Timing Diagram PCI_STOP asynchronous input to the ICS9248-192 used to turn off the PCICLK clocks for low power operation. PCI_STOP# is synchronized by the ICS9248-192 internally. The minimum that the PCICLK clocks are enabled (PCI_STOP# high pulse least 10 PCICLK clocks ...
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... The power down selection is used to put the part into a very low power state without turning off the power to the part. PD asynchronous active low input. This signal is synchronized internally by the ICS9248-192 prior to its control action of powering down the clock synthesizer. Internal clocks will not be running after the device is put in power down state ...
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... Select @ 66.6MHz pF; With input address to Vdd or L GND Logic Inputs X1 & X2 pins To 1st crossing of target Freq. From target Freq 1 1. ICS9248-192 +0 MIN TYP MAX 0 0.3 0 -200 15 80 600 11 14.318 ...
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... ICS9248-192 Electrical Characteristics - CPUCLK 70° 3.3 V +/-5 PARAMETER SYMBOL Output High Voltage V OH2B Output Low Voltage V OL2B Output High Current I OH2B Output Low Current I OL2B 1 Rise Time t r2B 1 Fall Time t f2B 1 Duty Cycle d t2B 1 Skew t sk2B 1 t jcyc-cyc2B Jitter ...
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... L CONDITIONS ICS9248-192 MIN TYP MAX UNITS 2.6 V 0 1 1000 ps 800 ps 500 ps 800 ps MIN TYP MAX UNITS 2.1 V 0 ...
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... ICS9248-192 4.40 mm. Body, 0.65 mm. pitch TSSOP (0.0256 Inch) (173 mil) Ordering Information ICS9248yG-192LF-T Example: ICS XXXX PPP 0540F—10/27/05 In Millimeters SYMBOL COMMON DIMENSIONS MIN 0.05 A2 0.80 b 0.19 c 0.09 SEE VARIATIONS D 6.40 BASIC 0.45 SEE VARIATIONS N α 0° aaa - VARIATIONS N MIN 28 9.60 Designation for tape and reel packaging ...
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... Revision History Rev. Issue Date Description F 10/27/2005 Added LF to Ordering Information 0540F—10/27/05 13 ICS9248-192 Page # 12 ...