ics9248-192 Integrated Device Technology, ics9248-192 Datasheet - Page 5
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ics9248-192
Manufacturer Part Number
ics9248-192
Description
Frequency Timing Generator For Transmeta Systems
Manufacturer
Integrated Device Technology
Datasheet
1.ICS9248-192.pdf
(13 pages)
Note: PWD = Power-Up Default
0540F—10/27/05
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit3
Bit1
Bit0
2,7:4
Bit
Bit
0-Frequency is seleced by hardware select. Latched input
1-Frequency is seleced by Bit 2, 7:4
0-Normal
0-Running 1-Tristate all outputs
Bit2
FS4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Hardware latch inputs can only access these frequencies
Bit7
FS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1-Spread spectrun Enabled
FS2
Bit6
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Bit5
FS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FS0
Bit4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
67.32
68.64
69.96
CPU
66.6
66.6
66.6
66.6
72.6
61.5
66.6
58.8
57.6
56.4
66.6
66.6
66.6
66.6
60
60
60
60
63
64
65
60
50
48
54
60
60
60
60
33.66
34.32
34.98
30.75
33.3
33.3
33.3
33.3
36.3
31.5
32.5
33.3
29.4
28.8
28.2
33.3
33.3
33.3
33.3
PCI
30
30
30
30
32
30
25
24
27
30
30
30
30
5
+/- 0.5% center spread
+/- 0.5% center spread
-0.6 % down spread
-0.8 % down spread
-1.0 % down spread
-0.6 % down spread
-0.8 % down spread
-1.0 % down spread
-1.6 % down spread
-1.8 % down spread
-2.0 % down spread
-1.6 % down spread
-1.8 % down spread
-2.0 % down spread
-0.4 % down spread
-0.4 % down spread
-1.4 % down spread
-1.4 % down spread
2% over-clocking
4% over-clocking
6% over-clocking
10% over-clocking
over-clocking
over-clocking
over-clocking
over-clocking
10% under-clock
2% under-clock
4% under-clock
6% under-clock
under-clocking
under-clocking
Spread %
00000
PWD
0
0
0
ICS9248-192