ics9248-50 Integrated Device Technology, ics9248-50 Datasheet

no-image

ics9248-50

Manufacturer Part Number
ics9248-50
Description
Frequency Timing Generator For Pentium Ii Systems
Manufacturer
Integrated Device Technology
Datasheet
Frequency Timing Generator for Pentium II Systems
Block Diagram
General Description
Power Groups
0278I—06/03/03
The ICS9248-50
Integrated
Circuit
Systems, Inc.
ICS9248-50
Features
Generates the following system clocks:
- 2 CPU (2.5V) up to 100MHz.
- 6 PCI (3.3V) @ 33.3MHz (Includes one free
running).
- 2 REF clks (3.3V) at 14.318MHz.
Skew characteristics:
- CPU – CPU<175ps
- PCI – PCI < 500ps
- CPU(early) – PCI = 1.5ns – 4ns.
Supports Spread Spectrum modulation for CPU and
PCI clocks, 0.5% down spread
Efficient Power management scheme through stop
clocks and power down modes.
Uses external 14.318MHz crystal, no external load
cap required for CL=18pF crystal.
28-pin (209 mil) SSOP package
Pin Configuration
28-Pin SSOP
ICS9248-50

Related parts for ics9248-50

ics9248-50 Summary of contents

Page 1

... Integrated Circuit Systems, Inc. Frequency Timing Generator for Pentium II Systems General Description The ICS9248-50 Block Diagram Power Groups 0278I—06/03/03 Features • Generates the following system clocks CPU (2.5V 100MHz PCI (3.3V) @ 33.3MHz (Includes one free running REF clks (3.3V) at 14.318MHz. • Skew characteristics: - CPU – ...

Page 2

... ICS9248-50 Pin Descriptions Pin number Pin name 1 GNDREF PCICLK_F 5,6,9,10,11 PCICLK (1:5) 7 GNDPCI 8 VDDPCI 12 VDD48 13 48 MHz 14 TS#/48/24MHz 15 GND48 16 SEL 100/66# 17 PD# 18 CPU_STOP# 19 VDD 20 PCI-Stop# 21 GND 22 GNDL 23,24 CPUCLK(1:0) 25 VDDL 26 REF1/SPREAD# 27 REF0/SEL48# 28 VDDREF 0278I—06/03/03 Type Power Ground for 14.318 MHz reference clock outputs Input 14 ...

Page 3

... Power Management Clock Enable Configuration ICS9248-50 Power Management Requirements ...

Page 4

... Notes: 1. All timing is referenced to the internal CPUCLK. 2. CPU_STOP asynchronous input and metastable conditions may exist. This signal is synchronized to the CPUCLKs inside the ICS9248-50. 3. All other clocks continue to run undisturbed. 4. PD# and PCI_STOP# are shown in a high (true) state. PCI_STOP# Timing Diagram Notes: 1 ...

Page 5

... All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device asynchronous input and metastable conditions may exist. This signal is synchronized inside the ICS9248. 3. The shaded sections on the VCO and the Crystal signals indicate an active clock is being generated. 0278I—06/03/03 ICS9248-50 5 ICS9248-50 ...

Page 6

... ICS9248-50 Absolute Maximum Ratings Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C Case Temperature . . . . . . . . . . . . . . . . . . . . . 0°C to +115°C Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C Electrical Characteristics - Input/Supply/Common Output Parameters 70°C; Supply Voltage PARAMETER SYMBOL Input High Voltage V IH Input Low Voltage V IL ...

Page 7

... 1.5 V, REF 1.5 V, REF 1 MHz 1 MHz T 7 ICS9248-50 MIN TYP MAX UNITS 1.8 2.3 V 0.31 0 0.4 1.15 1.6 ns 0.4 1.4 1 134 175 10.5 ns 186 200 ps -250 ...

Page 8

... ICS9248-50 Electrical Characteristics - PCICLK 70° 3.3 V +/-5 PARAMETER SYMBOL Output High Voltage V OH1 Output Low Voltage V OL1 Output High Current I OH1 Output Low Current I OL1 1 Rise Time Fall Time Duty Cycle Skew t sk1 t jcyc-cyc 1 Jitter t j1s t jabs 1 Guaranteed by design, not 100% tested in production ...

Page 9

... General Layout Precautions: Notes: Capacitor Values: 0278I—06/03/03 9 ICS9248-50 ...

Page 10

... ICS9248-50 Ordering Information 9248yF-50-T XXXX PPP - T Designation for tape and reel packaging Pattern Number ( digit number for parts with ROM code patterns) Package Type Revision Designator Device Type (consists digit numbers) 0278I—06/03/03 SYMBOL ...

Related keywords