ad80164absvz Analog Devices, Inc., ad80164absvz Datasheet - Page 29

• Manufacturer Part Number: ad80164absvz
• Description: Dual, 12-/14-/16-bit,1 Gsps Digital-to-analog Converters
• Manufacturer: Analog Devices, Inc.

Register Name
PLL Control
Misc Control
Hex
03
04
04
04
05
05
05
06
06
07
07
07
07
08
08
09
09
09
09
0A
0A
Address
Decimal
3:0
7:4
3:1
0
7:4
3:1
0
7:4
3:0
7
6
5
4:0
7:2
1:0
7
6:5
4:3
2:0
7:5
4:0
Description
Data delay timing margin<3:0>
Data clock delay LSBs<3:0>
Output SYNC pulse divide<2:0>
Sync out delay<4>
Sync out delay<3:0>
Input sync pulse frequency
ratio<2:0>
Sync input delay<4>
Sync input delay<3:0>
Input sync pulse timing error
tolerance<3:0>
SYNC receiver enable
Sync driver enable
Sync triggering edge
Data clock offset<4:0>
PLL band select<5:0>
PLL VCO AGC gain<10>
PLL enable
PLL VCO divider ratio<1:0>
PLL loop divide ratio<1:0>
PLL bias setting<2:0>
PLL control voltage range<2:0>
PLL loop bandwidth
adjustment<4:0>
Rev. 0 Page 29 of 68
Function
See Table 21
Sets delay of REFCLK in to DATACLK out
The frequency of the SYNC_O signal is
equal to f
000: N = 32
001: N = 16
010: N = 8
011: N = 4
100: N = 2
101: N = 1
110: N = undefined
111: N = undefined
Sync output delay, Bit 4
Sync output delay, Bits<3:0> The delay line
resolution is 180 ps per step
Input sync pulse frequency divider, see the
AN-822 application note
Sync input delay, Bit 4
See the Multiple DAC Synchronization
section for details on using these registers
to synchronize multiple DACs
0: SYNC_O changes on REFCLK falling edge
1: SYNC_O changes on REFCLK rising edge
VCO frequency range vs. PLL band select
value (see Table 19)
Leave at default value for optimal
performance
0: PLL off, DAC rate clock supplied by
outside source
1: PLL on, DAC rate clock synthesized
internally from external reference clock via
PLL clock multiplier
FVCO/f
f
Set to 011 for optimal performance
000 to 111, proportional to voltage at PLL
loop filter output, readback only
See PLL Loop Filter Bandwidth section for
details, optimally set at 0x0F
DAC
00 × 1
01 × 2
10 × 4
11 × 8
00 × 2
01 × 4
10 × 8
11 × 16
/f
REF
DAC
DAC
AD9776A/AD9778A/AD9779A
/N, where N is set as follows:
Default
0000
0000
000
0000
000
0
0
0
0
0
0
0
111001
11
0
10
10
010
000
11111