ad80164absvz Analog Devices, Inc., ad80164absvz Datasheet - Page 48

• Manufacturer Part Number: ad80164absvz
• Description: Dual, 12-/14-/16-bit,1 Gsps Digital-to-analog Converters
• Manufacturer: Analog Devices, Inc.

AD9776A/AD9778A/AD9779A
detect setting in the SPI register (Register 3, Bits<3:0>). IRQ
is set when the timing margin between the input data and
DATACLK out (minus the programmable margin) violates the
setup and hold times given in Table 20. Improvement in setup
time can therefore be achieved by reducing the DATACLK delay,
and improvement in hold time can be achieved by increasing
DATACLK delay. Also, note that if an IRQ is set, it does not
reset itself if the IRQ fault is resolved. To reset the IRQ, a 0
must be written to the IRQ register.
DATA DELAY LINE, ERROR CORRECTION
AUTO MODE
The data delay error correction can also be run in an automatic
mode where the AD9776A/AD9778A/AD9779A determines
the optimal timing and set the data delay accordingly. The value
in the DATA DELAY register can then be read back by the user
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if necessary. In auto mode, the timing margin window must still
be programmed by the user.
In operation, the autotiming mode can be left on and tracks
with temperature with no other user intervention.
MULTIPLE DAC SYNCHRONIZATION
The AD9776A/AD9778A/AD9779A have programmable
features that allow the CMOS digital data bus inputs and
internal filers on multiple devices to be synchronized. This
means that the DATACLK output signal on an AD9776A/
AD9778A/AD9779A can be used to register the output data
for a data bus delivering data to multiple AD9776A/AD9778A/
AD9779As. The details of this operation are given in Analog
Devices Application Note AN-822.