ad80164absvz Analog Devices, Inc., ad80164absvz Datasheet - Page 43

• Manufacturer Part Number: ad80164absvz
• Description: Dual, 12-/14-/16-bit,1 Gsps Digital-to-analog Converters
• Manufacturer: Analog Devices, Inc.

POWER-DOWN AND SLEEP MODES
The AD9776A/AD9778A/AD9779A have a variety of power-
down modes, so that the digital engine, main TxDACs, or
auxiliary DACs can be powered down individually or together.
Via the SPI port, the main TxDACs can be placed in sleep or
power-down mode. In sleep mode, the TxDAC output is turned
off, thus reducing power dissipation. The reference remains
powered on, however, so that recovery from sleep mode is very
fast. With the power-down mode bit set (Register 0x00, Bit 4), all
analog and digital circuitry, including the reference, is powered
down. The SPI port remains active in this mode. This mode
offers more substantial power savings than sleep mode, but the
turn-on time is much longer. The auxiliary DACs also have the
capability to be programmed into sleep mode via the SPI port.
The auto power-down enable bit (Register 0x00, Bit 3) controls
the power-down function for the digital section of the devices.
The auto power-down function works in conjunction with the
TXENABLE pin (Pin 39) according to the following:
TXENABLE (Pin 39) =
or TXENABLE (Pin 39) =
As shown in Figure 92, the power dissipation saved by using the
power-down mode is nearly proportional to the duty cycle of
the signal at the TXENABLE pin.
If the TxEnable Invert bit (Register 0x02, Bit 1) is set, the
function of this TXENABLE pin is inverted.
0: autopower-down enable =
1: normal operation.
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
Figure 92. Power Savings Based on Duty Cycle of TXENABLE
0
0
0: flush data path with 0s
1: flush data for multiple REFCLK cycles; then
automatically place the digital engine in power-down
state. DACs, reference, and SPI port are not affected.
20
DUTY CYCLE (%)
40
60
2× INT
2× INT
4× INT
4× INT
8× INT
8× INT
f
f
f
f
f
f
DATA
DATA
DATA
DATA
DATA
DATA
80
= 50MSPS
= 200MSPS
= 50MSPS
= 200MSPS
= 50MSPS
= 200MSPS
100
Rev. 0 Page 43 of 68
INTERLEAVED DATA MODE
The TxEnable bit is a dual functioning bit. In dual port mode,
it is simply used to power down the digital section of the
devices. In interleaved mode, TxEnable acts as an IQSELECT
signal and indicates to which DAC the P1D data is targeted.
The IQSELECT signal should be time aligned with the input
data. When IQSELECT is high the corresponding data-word is
sent to the I DAC and when IQSELECT is low the corresponding
data is sent to the Q DAC. The timing of the digital interface in
interleaved mode is shown in Figure 93.
The Q First bit (Register 0x02, Bit 0) controls the pairing
order of the input data. With the Q First bit set to the default
of 0, the IQ pairing sent to the DACs is the two input data
words corresponding to IQSELECT low followed by IQSELECT
high. With Q First set to 1, the IQ pairing sent to the DACs is
the two input data-words corresponding to IQSELECT high
followed by IQSELECT low. Note that with Q First set, the I
data still corresponds to the IQSELECT high word and the
Q data corresponds to the IQSELECT low word and only the
pairing changes.
If TXENABLE is brought low and held low for multiple REFCLK
cycles, then the devices flush the data in the interpolation
filters, and shut down the digital engine after the filters are
flushed. The number of REFCLK cycles it takes to go into this
power-down mode is a function of the length of the equivalent
2×, 4×, or 8× interpolation filter.
TIMING INFORMATION
Figure 94 to Figure 97 show some of the various timing possi-
bilities when the PLL is enabled. The combination of the settings
of N
frequency (f
rate. Figure 94 to Figure 97 show what the timing looks like
when N
In interleaved mode, set up and hold times of DATACLK out
with respect to the data inputs are the same as those shown in
Figure 94 to Figure 97. It is recommended that any toggling of
TXENABLE occur concurrently with the digital data input
transitions. In this way, timing margins between DATACLK,
TXENABLE, and digital input data are optimized.
QFIRST = 0
QFIRST = 1
2
P1D_SMP<15:0>
and N
QDAC<15:0>
QDAC<15:0>
2
IQSEL_SMP
IDAC<15:0>
IDAC<15:0>
/N
P1D<15:0>
IQSELECT
DATACLK
SMP_CLK
Figure 93. Interleaved Mode Digital Interface Timing
3
3
REFCLK
= 1 (N
from Figure 74 means that the reference clock
) can be a multiple of the actual input data
AD9776A/AD9778A/AD9779A
2
P1D(1)
= N
P1D(1)
3
P1D(2)
= interpolation rate).
P1D(2)
PID(3)
PID(3)
PID(4)
P1D(1)
P1D(2)
P1D(1)
PID(4)
PID(5)
PID(5)
PID(6)
PID(3)
PID(4)
PID(3)
PID(4)
PID(6)
PID(7)
PID(7)
PID(8)
PID(5)
PID(6)
PID(5)
PID(6)
PID(8)