lmk03000c National Semiconductor Corporation, lmk03000c Datasheet - Page 14

• Manufacturer Part Number: lmk03000c
• Description: Precision Clock Conditioner With Integrated Vco
• Manufacturer: National Semiconductor Corporation

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2.3 REGISTER R0 to R7
Registers R0 through R7 control the eight clock outputs. Register R0 controls CLKout0, Register R1 controls CLKout1, and so on.
There is one additional bit in register R0 called RESET. Aside from this, the functions of these bits are identical. The X in
CLKoutX_MUX, CLKoutX_DIV, CLKoutX_DLY, and CLKoutX_EN denote the actual clock output which may be from 0 to 7.
2.3.1 RESET bit -- R0 only
This bit is only in register R0. The use of this bit is optional and it should be set to '0' if not used. Setting this bit to a '1' forces all
registers to their power on reset condition and therefore automatically clears this bit. If this bit is set, all other R0 bits are ignored
and R0 needs to be programmed again if used with its proper values and RESET = 0.
2.3.2 CLKoutX_MUX[1:0] -- Clock Output Multiplexers
These bits control the Clock Output Multiplexer for each clock output. Changing between the different modes changes the blocks
in the signal path and therefore incurs a delay relative to the bypass mode. The different MUX modes and associated delays are
listed below.
RESET
CLKoutX_MUX
CLKoutX_EN
CLKoutX_DIV
CLKoutX_DLY
DIV4
OSCin_FREQ
VCO_R4_LF
VCO_R3_LF
VCO_C3_C4_LF
EN_Fout
EN_CLKout_Global
POWERDOWN
PLL_MUX
PLL_R
PLL_CP_GAIN
VCO_DIV
PLL_N
Bit Name
CLKoutX_MUX[1:0]
0
1
2
3
Bit Value
Default
760
10
10
0
0
0
1
0
0
0
0
0
0
1
0
0
0
2
No reset, normal operation
Bypassed
Disabled
Divide by 2
0 ps
PDF
10 MHz OSCin
Low (~200 Ω)
Low (~600 Ω)
C3 = 0 pF, C4 = 10 pF
Fout disabled
Normal - CLKouts normal
Normal - Device active
Disabled
R divider = 10
100 uA
Divide by 2
N divider = 760
≤
20 MHz
Bit State
Divided and Delayed
Bypassed (default)
Delayed
Divided
Mode
14
Reset to power on defaults
CLKoutX mux mode
CLKoutX enable
CLKoutX clock divide
CLKoutX clock delay
Phase Detector Frequency
OSCin Frequency in MHz
R4 internal loop filter values
R3 internal loop filter values
C3 and C4 internal loop filter values
Fout enable
Global clock output enable
Device power down
Multiplexer control for LD pin
PLL R divide value
Charge pump current
VCO divide value
PLL N divide value
Bit Description
Added Delay Relative to Bypass Mode
(In addition to the programmed delay)
(In addition to the programmed delay)
100 ps
400 ps
500 ps
0 ps
Register
R0 to R7
R11
R13
R14
R15
R0
Location
18:17
21:14
13:11
23:20
31:30
29:26
15:8
10:8
19:8
25:8
7:4
7:4
Bit
31
16
15
28
27
26