lmk03000c National Semiconductor Corporation, lmk03000c Datasheet - Page 15
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lmk03000c
Manufacturer Part Number
lmk03000c
Description
Precision Clock Conditioner With Integrated Vco
Manufacturer
National Semiconductor Corporation
Datasheet
1.LMK03000C.pdf
(26 pages)
2.3.3 CLKoutX_DIV[7:0] -- Clock Output Dividers
These bits control the clock output divider value. In order for these dividers to be active, the respective CLKoutX_MUX (See 2.3.2)
bit must be set to either "Divided" or "Divided and Delayed" mode. After all the dividers are programed, the SYNC* pin must be
used to ensure that all edges of the clock outputs are aligned (See 1.7). The Clock Output Dividers follow the VCO Divider so the
final clock divide for an output is VCO Divider × Clock Output Divider. By adding the divider block to the output path a fixed delay
of approximately 100 ps is incurred.
The actual Clock Output Divide value is twice the binary value programmed as listed in the table below.
2.3.4 CLKoutX_DLY[3:0] -- Clock Output Delays
These bits control the delay stages for each clock output. In order for these delays to be active, the respective CLKoutX_MUX
(See 2.3.2) bit must be set to either "Delayed" or "Divided and Delayed" mode. By adding the delay block to the output path a fixed
delay of approximately 400 ps is incurred in addition to the delay shown in the table below.
2.3.5 CLKoutX_EN bit -- Clock Output Enables
These bits control whether an individual clock output is enabled or not. If the EN_CLKout_Global bit (See 2.6.4) is set to zero or if
GOE pin is held low, all CLKoutX_EN bit states will be ignored and all clock outputs will be disabled. See 1.8 for more information
on CLKout states.
0
0
0
0
0
0
1
.
CLKoutX_EN bit
0
0
0
0
0
0
1
.
0
1
CLKoutX_DLY[3:0]
0
0
0
0
0
0
1
.
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
CLKoutX_DIV[7:0]
0
0
0
0
0
0
1
.
GOE pin = High / No Connect
EN_CLKout_Global bit = 1
0
0
0
0
0
0
1
.
Conditions
15
0
0
0
0
1
1
1
.
0
0
1
1
0
0
1
.
0
1
0
1
0
1
1
.
Delay (ps)
0 (default)
1050
1200
1350
1500
1650
1800
1950
2100
2250
150
300
450
600
750
900
Clock Output Divider value
Disabled (default)
CLKoutX State
Enabled
2 (default)
Invalid
510
10
...
4
6
8
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