max9257agcm/v+ Maxim Integrated Products, Inc., max9257agcm/v+ Datasheet - Page 27

• Manufacturer Part Number: max9257agcm/v+
• Description: Fully Programmable Serializer/deserializer With Uart/i2c Control Channel
• Manufacturer: Maxim Integrated Products, Inc.

Figure 21. Simplified Modulation Profile for the MAX9257A/
MAX9258A
Terminate the LVDS link at both ends with the charac-
teristic impedance of the transmission line (typically
100O differential). The LVDS inputs and outputs are high
impedance to GND and differentially.
The devices each have spread-spectrum options. Both
should not be turned on at the same time. When the
MAX9257A is programmed for spread spectrum, the
MAX9258A tracks and passes the spread to its clock and
data outputs. The MAX9257A/MAX9258A are both center
spread
spread spectrum, but has slower transition times.
The MAX9258A features a programmable spread-spec trum
clock and data outputs for reduced EMI. The sin gle-ended
data outputs are programmable for no spread, Q2%, or
Q4% (see the
recovered pixel clock fre quency. The output spread is pro-
grammed in register REG1[7:6].
options, and
The MAX9257A features programmable spread spec-
trum for the LVDS outputs.
spread options, and
lation rates. Only one device (the MAX9257A or the
MAX9258A) should be programmed for spread spectrum
at a time. If the MAX9257A is programmed for spread,
the MAX9258A tracks and passes the spread to the data
and clock out puts. The PRATE range of 00 and 01 (5MHz
≤ PCLK ≤ 20MHz) supports all the spread options. The
PRATE range of 10 and 11 (20MHz ≤ PCLK ≤ 70MHz)
requires that the spread be 2% or less.
f
SPREAD
f
SPREAD
f
(Figure
PCLK_IN
(MAX)
(MIN)
Table 18
FREQUENCY
Typical Operating
21). The control channel does not use
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Fully Programmable Serializer/Deserializer
Table 20
Spread-Spectrum Selection
shows the various modulation rates.
MAX9258A Spread Spectrum
MAX9257A Spread Spectrum
1/f
SSM
Characteristics) around the
Table 17
Table 19
shows the various modu-
LVDS Termination
shows the spread
shows various
with UART/I
TIME
Table 16. Parallel-Word Width
Table 17. MAX9258A Spread
Table 18. MAX9258A Modulation Rate
Table 19. MAX9257A LVDS Output Spread
The MAX9257A has a PLL to filter high-frequency pixel
clock jitter on PCLK_IN. The FPLL can be bypassed by
writing 1 to REG4[2]. The FPLL improves the MAX9258A’s
data recovery by filtering out the high-fre quency compo-
nents from the pixel clock that the MAX9258A cannot
track. The 3dB bandwidth of the FPLL is 100kHz (typ).
(REG1[7:6])
PARALLEL-WORD WIDTH
PRATE
PRATE (REG1[7:6])
MAX9257A/MAX9258A
00
01
10
11
REG1[7:5]
2
000
001
010
011
100
101
110
111
00
01
10
11
10
12
14
16
18
C Control Channel
MODULATION RATE
PCLK/1040
PCLK/1248
PCLK/312
PCLK/520
Pixel Clock Jitter Filter
PWIDTH (REG0[2:0])
SPREAD (%)
SPREAD (%)
f SSM RANGE (kHz)
Q1.75
Q1.5
Q3.5
000
001
010
011
1XX
19.2 to 38.5
19.2 to 38.5
Off
Off
Q2
Q4
Off
Off
Q2
Q3
Q4
16 to 32
32 to 56