max9257agcm/v+ Maxim Integrated Products, Inc., max9257agcm/v+ Datasheet - Page 34

• Manufacturer Part Number: max9257agcm/v+
• Description: Fully Programmable Serializer/deserializer With Uart/i2c Control Channel
• Manufacturer: Maxim Integrated Products, Inc.

When REM is grounded, the MAX9257A fully pow-
ers up when power is applied. The power-down bit
PD (REG4[4]) is disabled and serialization bit SEREN
(REG4[3]) is enabled. If PCLK_IN is not running, the
MAX9257A stays in the control channel. After PCLK_IN
is applied, the control channel times out due to STO,
ETO, or EF. The MAX9257A starts the handshaking after
the MAX9257A locks to PCLK after 32,768 clock cycles.
If PCLK_IN is running, serialization starts automatically
after PLL of the MAX9257A locks to PCLK_IN with default
values in the registers.
When REM is pulled up to V
up in a low power state, drawing less than 100FA supply
current. To wake-up the MAX9257A, the ECU first trans-
mits a dummy frame 0xDB and then waits at least 100Fs
to allow the MAX9257A’s internal analog circuitry to fully
power up. Then the ECU configures the MAX9257A reg-
isters, including a write to disable the PD bit (REG4[4])
so that the MAX9257A does not return back to the low
power state. Every packet needs to start with a synchro-
nization frame (see the
disabled within 70ms after transmitting the dummy frame,
the MAX9257A returns to the low power state and the
whole power-up sequence needs to be repeated. After
configuration is complete, the ECU also needs to enable
the SEREN bit to start the video phase.
At initial power-up with REM pulled to V
of SEREN bit is 0, so STO and ETO timers are not active.
Control channel is enabled as long as SEREN is 0. This
allows the control channel to be used for extensive pro-
gramming at initial power-up without the channel timing
out. UART, parity, framing and packet errors in the con-
trol channel communications are reported if end frame is
used to close control channel (see the
Checking and Reporting
of errors, verify every write com mand by reading back
the registers before enabling serialization.
When the control channel is open, the ECU writes to the
PD bit to power down the MAX9257A. In this case, to
power up the MAX9257A again, the power-up sequence
explained in the
(REM = Pulled Up to V
The MAX9258A has a PD input that powers down the device.
Powering the MAX9257A with Serialization Enabled
���������������������������������������������������������������� Maxim Integrated Products 34
Remote Power-Up of the MAX9257A
Remote Power-Up of the MAX9257A
Fully Programmable Serializer/Deserializer
CC
UART
section). For faster identification
)
(REM = Ground at Power-Up)
section needs to be repeated.
(REM = Pulled Up to V
CC
sec tion). If the PD bit is not
, the MAX9257A wakes
Link Power-Down
CC
MAX9258A Error
, default value
with UART/I
CC
)
The MAX9258A has an open-drain ERROR output. This
output indicates various error conditions encountered
during the operation of the system. When an error con-
dition is detected and needs to be reported, ERROR
asserts low. ERROR indicates three error conditions:
UART, video parity, and PRBS errors.
During control channel communication in base mode, the
devices record UART frame, parity, and packet errors.
I
interface is enabled. If ECU closes the control channel
by using end frame (EF), the MAX9257A sends a special
internal UART frame back to the MAX9258A called error
frame. The MAX9257A UART and I
the next control channel. The MAX9258A receives the
error frame and records the error status in its UART error
register (REG13). ECU must use end frame to the close
control channel for the MAX9257A to report back UART
and I
bits in the UART error register is 1, ERROR asserts low.
The UART error regis ter is reset when ECU reads it, and
ERROR deasserts high immediately if UART errors were
the only reason that ERROR was asserted low. If the
MAX9258A is not locked (LOCK = low), UART error is not
reported.
When video parity check is enabled (REG0[3] in both
devices), the MAX9258A counts the number of video
pari ty errors by checking recovered video words. Value
of this counter is reflected in PAERRHI (8 MSB bits,
REG11) and PAERRLO (8 LSB bits, REG10). If the num-
ber of detected parity errors is greater than or equal
to the parity error threshold PATHRHI (REG9) and
PATHRLO (REG8), then ERROR asserts low. In this case,
ERROR deasserts high after next video phase starts if
video parity errors were the only reason that ERROR was
asserted low. To report parity errors in bypass mode,
program autoerror reset (AER) to 1 (REG1[5] = 1).
The default method to reset errors is to read the respec-
tive error registers in the MAX9258A (registers 10, 11,
and 13). If errors were present before the next control
chan nel, the error count gets incremented to the previ-
ous number. By setting the autoerror reset (AER) bit to 1,
the error registers reset when the control channel ends.
Setting AER to 1 does not reset PRBS errors.
2
C errors are also recorded by MAX9257A when I
MAX9258A Error Checking and Reporting
MAX9257A/MAX9258A
2
C errors to the MAX9258A. Whenever one of the
2
C Control Channel
2
C errors are reset at
Video Parity Errors
Autoerror Reset
UART Errors
2
C