max9257agcm/v+ Maxim Integrated Products, Inc., max9257agcm/v+ Datasheet - Page 29

• Manufacturer Part Number: max9257agcm/v+
• Description: Fully Programmable Serializer/deserializer With Uart/i2c Control Channel
• Manufacturer: Maxim Integrated Products, Inc.

The MAX9257A features programmable preemphasis
where extra current is added when the LVDS outputs
transition on the serial link. Preemphasis provides addi-
tional current to the normal drive current. For example,
20% preemphasis provides 20% greater current than
the normal drive current. Current is boosted only on the
transitions and returns to the normal drive current after
switching. Select the preemphasis level to optimize the
eye diagram. Preemphasis boosts the high-frequency
content of the LVDS outputs to enable driving greater
cable lengths. The amount of preemphasis is pro-
grammed in REG12[7:5]
PCLK: The MAX9257A is programmable to latch data
on either rising or falling edge of PCLK. The polarity of
PCLKOUT at the MAX9258A can be independent of the
MAX9257A PCLK active edge. The polarity of PCLK can
be programmed using REG4[5] of the MAX9257A and
the MAX9258A.
VSYNC: The MAX9257A and the MAX9258A enter con-
trol channel on the falling edge of VSYNC. The default
reg ister settings are VSYNC active falling edge for both
the MAX9257A and the MAX9258A. If the VSYNC active
edge is programmed for rising edge at the MAX9257A,
the MAX9258A VSYNC active edge must also be pro-
grammed for rising edge to reproduce VSYNC rising
edge at the MAX9258A output. However, matching
the polarity of the VSYNC active edge between the
MAX9257A and the MAX9258A is not a requirement for
proper operation.
HSYNC: HSYNC active-edge polarity is programmable
for the MAX9258A.
The MAX9257A has up to 10 GPIOs available. GPIO8 and
GPIO9 are always available while GPIO[0:7] are avail-
able depending on the parallel-word width
If GPIOs are not available, the corresponding GPIO bits
are not used.
A GPIO can be programmed to drive an LVCMOS logic level
or to read a logic input. The register bit that sets the output
level when the GPIO is programmed as an output stores the
input level when the GPIO is programmed as an input.
VSYNC, HSYNC, and Pixel Clock Polarity
LVDS Output Preemphasis (SDO±)
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General-Purpose I/Os (GPIOs)
Fully Programmable Serializer/Deserializer
(Table
21).
(Table
with UART/I
22).
Table 21. Preemphasis
Table 22. GPIOs vs. Parallel-Word Width
LOCK and ERROR are open-drain outputs that require a
pullup resistor to an external supply. ERROR asserts low
when an error occurs and LOCK is high impedance when
the MAX9258A is locked to the MAX9257A and remains
high under the locked condition. When the devices are
in shutdown, the channel is not locked and LOCK goes
high impedance, is pulled high, and should be ignored.
ERROR is high impedance at shutdown and remains
high. In choosing pullup resistors, there is a tradeoff
between power dissipation and speed; 10kI pullup
should be sufficient.
The LOCK and ERROR outputs can be wired in an AND
configuration if you have multiple serializers and deserial-
izers, or a single serializer fanned out to multi ple deseri-
alizers through a repeater. For such situa tions, wire the
multiple LOCK outputs together and use a single pullup
resistor to pull up all the lines high. LOCK is high if all
the devices are locked. Do the same thing for ERROR;
ERROR is low if any MAX9258A reports errors.
PARALLEL-WORD WIDTH (N)
MAX9257A/MAX9258A
000,101,110
REG12[7:5]
Open-Drain Outputs (LOCK, ERROR)
2
001
010
011
100
111
18
16
14
12
10
C Control Channel
PREEMPHASIS (%)
GPIOs AVAILABLE
GPIO[8:9]
GPIO[6:9]
GPIO[4:9]
GPIO[2:9]
GPIO[0:9]
100
20
40
60
80
0