pcf2123 NXP Semiconductors, pcf2123 Datasheet - Page 24

• Manufacturer Part Number: pcf2123
• Description: Spi Real Time Clock/calendar
• Manufacturer: NXP Semiconductors

NXP Semiconductors
PCF2123_1
Product data sheet
9.8.3 Timer flags
9.9 Interrupt output
When a minute or second interrupt occurs, bit MSF is set to logic 1. Similarly, at the end of
a timer countdown or alarm event, bit TF or AF are set to logic 1. These bits maintain their
value until overwritten by software. If both countdown timer and minute or second
interrupts are required in the application, the source of the interrupt can be determined by
reading these bits. To prevent one flag being overwritten while clearing another a logical
AND is performed during a write access. Writing a logic 1 will cause the flag to maintain its
value, whilst writing a logic 0 will cause the flag to be reset.
Three examples are given for clearing the flags. Clearing the flags is made by a write
command, therefore bits 7, 6, 4, 1 and 0 must be written with their previous values.
Repeatedly re-writing these bits has no influence on the functional behavior.
Table 30.
Table
appropriate flag.
Table 31.
Table 32.
Table 33.
Clearing the alarm flag (bit AF) operates in exactly the same way, see
An active LOW interrupt signal is available at pin INT. Operation is controlled via the bits
of register Control_2. Interrupts may be sourced from four places: second and minute
timer, countdown timer, alarm function or offset function.
With bit TI_TP, the timer generated interrupts can be configured to either generate a pulse
or to follow the status of the interrupt flags (bits TF and MSF). Correction interrupt pulses
are always
Register
Control_2
Register
Control_2
Register
Control_2
Register
Control_2
31,
Table 32
Flag location in register Control_2
Example to clear only TF (bit 2) in register Control_2
Example to clear only MSF (bit 5) in register Control_2
Example to clear both TF and MSF (bit 2 and bit 5) in register Control_2
1
128
Bit
7
-
Bit
7
-
Bit
7
-
Bit
7
-
second long. Alarm interrupts always follow the condition of AF.
and
Rev. 01 — 19 November 2008
Table 33
6
-
6
-
6
-
6
-
show what instruction must be sent to clear the
5
MSF
5
1
5
0
5
0
4
-
4
-
4
-
4
-
3
AF
3
1
3
1
3
1
SPI Real time clock/calendar
2
TF
2
0
2
1
2
0
Section
PCF2123
© NXP B.V. 2008. All rights reserved.
1
-
1
-
1
-
1
-
9.7.1.
0
-
0
-
0
-
0
-
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