m48t37v STMicroelectronics, m48t37v Datasheet - Page 10

• Manufacturer Part Number: m48t37v
• Description: 5.0 Or 3.3v, 256 Kbit 32 Kbit X 8 Timekeeper Sram
• Manufacturer: STMicroelectronics

2.2
10/29
Write mode
The M48T37Y/V is in the WRITE Mode whenever W and E are low. The start of a WRITE is
referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the
earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W
must return high for a minimum of t
prior to the initiation of another READ or WRITE cycle. Data-in must be valid t
the end of WRITE and remain valid for t
WRITE cycles to avoid bus contention; however, if the output bus has been activated by a
low on E and G, a low on W will disable the outputs t
Figure 5.
Figure 6.
A0-A14
E
W
DQ0-DQ7
A0-A14
E
W
DQ0-DQ7
Write enable controlled, write AC waveform
Chip enable controlled, write AC waveforms
tAVEL
tAVEL
tAVWL
tAVWL
tWLQZ
EHAX
WHDX
tAVWH
from Chip Enable or t
tAVEH
tWLWH
tAVAV
VALID
tAVAV
VALID
tELEH
afterward. G should be kept high during
tDVEH
WLQZ
tDVWH
DATA INPUT
DATA INPUT
after W falls.
tWHDX
WHAX
from WRITE Enable
tEHDX
tWHQX
tEHAX
tWHAX
DVWH
AI00926
AI00927
prior to