m48t37v STMicroelectronics, m48t37v Datasheet - Page 8

• Manufacturer Part Number: m48t37v
• Description: 5.0 Or 3.3v, 256 Kbit 32 Kbit X 8 Timekeeper Sram
• Manufacturer: STMicroelectronics

2
Note:
2.1
8/29
Operation modes
As
oscillator of the M48T37Y/V are integrated on one silicon chip. The memory locations that
provide user accessible BYTEWIDE™ clock information are in the bytes with addresses
7FF1 and 7FF9h-7FFFh (located in
century, year, month, date, day, hour, minute, and second in 24 hour BCD format.
Corrections for 28, 29 (leap year - valid until the year 2100), 30, and 31 day months are
made automatically.
Byte 7FF8h is the clock control register. This byte controls user access to the clock
information and also stores the clock calibration setting.
Byte 7FF7h contains the watchdog timer setting. The watchdog timer redirects an out-of-
control microprocessor and provides a reset or interrupt to it. Bytes 7FF2h-7FF5h are
reserved for clock alarm programming. These bytes can be used to set the alarm. This will
generate an active low signal on the IRQ/FT pin when the alarm bytes match the date,
hours, minutes, and seconds of the clock. The eight clock bytes are not the actual clock
counters themselves; they are memory locations consisting of BiPORT™ READ/WRITE
memory cells. The M48T37Y/V includes a clock control circuit which updates the clock
bytes with current information once per second. The information can be accessed by the
user in the same manner as any other location in the static memory array.
The M48T37Y/V also has its own Power-fail Detect circuit. The control circuitry constantly
monitors the single V
tolerance, the circuit write protects the SRAM, providing a high degree of data security in the
midst of unpredictable system operation brought on by low V
Battery Back-up Switchover Voltage (V
maintains data and clock operation until valid power returns.
Table 2.
1. See
X = V
Read mode
The M48T37Y/V is in the READ Mode whenever WRITE Enable (W) is high and Chip
Enable (E) is low. The unique address specified by the 15 Address Inputs defines which one
of the 32,752 bytes of data is to be accessed. Valid data will be available at the Data I/O
pins within Address Access time (t
Deselect
WRITE
READ
READ
Deselect
Deselect
Figure 3 on page 7
Mode
IH
Table 13 on page 23
or V
IL
Operating modes
; V
V
SO
SO
4.5 to 5.5V
3.0 to 3.6V
to V
= Battery Back-up Switchover Voltage.
CC
V
V
PFD
shows, the static memory array and the quartz controlled clock
or
SO
CC
for details.
supply for an out of tolerance condition. When V
(1)
(min)
(1)
AVQV
Table 5 on page
V
V
V
V
SO
E
X
X
) after the last address input signal is stable,
IH
IL
IL
IL
), the control circuitry connects the battery which
V
V
G
X
X
X
X
IH
IL
13). The clock locations contain the
V
V
V
W
X
X
X
IH
IH
IL
CC
DQ0-DQ7
. As V
High Z
High Z
High Z
High Z
D
D
OUT
IN
CC
falls below the
CC
Battery Back-up
CMOS Standby
is out of
Standby
Power
Active
Active
Active
Mode