m48t37v STMicroelectronics, m48t37v Datasheet - Page 12

• Manufacturer Part Number: m48t37v
• Description: 5.0 Or 3.3v, 256 Kbit 32 Kbit X 8 Timekeeper Sram
• Manufacturer: STMicroelectronics

3
3.1
3.2
Note:
3.3
Note:
12/29
Clock operations
Reading the clock
Updates to the TIMEKEEPER
prevent reading data in transition. The BiPORT™ TIMEKEEPER cells in the RAM array are
only data registers and not the actual clock counters, so updating the registers can be
halted without disturbing the clock itself.
Updating is halted when a '1' is written to the READ Bit, D6 in the Control Register 7FF8h.
As long as a '1' remains in that position, updating is halted. After a halt is issued, the
registers reflect the count; that is, the day, date, and the time that were current at the
moment the halt command was issued.
All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an
update in progress. Updating will resume within a second after the bit is reset to a '0.'
Setting the clock
Bit D7 of the Control Register (7FF8h) is the WRITE Bit. Setting the WRITE Bit to a '1,' like
the READ Bit, halts updates to the TIMEKEEPER registers. The user can then load them
with the correct day, date, and time data in 24 hour BCD format (see
Resetting the WRITE Bit to a '0' then transfers the values of all time registers (7FF1h,
7FF9h-7FFFh) to the actual TIMEKEEPER counters and allows normal operation to
resume. After the WRITE Bit is reset, the next clock update will occur in approximately one
second.
Upon power-up following a power failure, both the WRITE Bit and the READ Bit will be reset
to '0.'
Stopping and starting the oscillator
The oscillator may be stopped at any time. If the device is going to spend a significant
amount of time on the shelf, the oscillator can be turned off to minimize current drain on the
battery. The STOP Bit is the MSB of the seconds register. Setting it to a '1' stops the
oscillator. When reset to a '0,' the M48T37Y/V oscillator starts within one second.
It is not necessary to set the WRITE Bit when setting or resetting the FREQUENCY TEST
Bit (FT) or the STOP Bit (ST).
®
registers should be halted before clock data is read to
Table 5 on page
13).