m48t37v STMicroelectronics, m48t37v Datasheet - Page 15

• Manufacturer Part Number: m48t37v
• Description: 5.0 Or 3.3v, 256 Kbit 32 Kbit X 8 Timekeeper Sram
• Manufacturer: STMicroelectronics

3.5
Figure 8.
Calibrating the clock
The M48T37Y/V is driven by a quartz controlled oscillator with a nominal frequency of
32,768 Hz. The devices are tested not to exceed ±35 PPM (parts per million) oscillator
frequency error at 25 °C, which equates to about ±1.53 minutes per month. With the
calibration bits properly set, the accuracy of each M48T37Y/V improves to better than +1/–2
PPM at 25 °C.
The oscillation rate of any crystal changes with temperature (see
Most clock chips compensate for crystal frequency and temperature shift error with
cumbersome trim capacitors. The M48T37Y/V design, however, employs periodic counter
correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit
at the divide by 256 stage, as shown in
are blanked (subtracted, negative calibration) or split (added, positive calibration) depends
upon the value loaded into the five-bit Calibration byte found in the Control Register. Adding
counts speeds the clock up, subtracting counts slows the clock down.
The Calibration Byte occupies the five lower order bits (D4-D0) in the Control Register
7FF8h. These bits can be set to represent any value between 0 and 31 in binary form. Bit
D5 is the Sign Bit; '1' indicates positive calibration, '0' indicates negative calibration.
Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per
minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If
a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be
modified; if a binary 6 is loaded, the first 12 will be affected, and so on.
Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator
cycles for every 125, 829, 120 (64 minutes x 60 seconds/minute x 32,768 cycles/second)
actual oscillator cycles, that is +4.068 or –2.034 PPM of adjustment per calibration step in
the calibration register. Assuming that the oscillator is in fact running at exactly 32,768 Hz,
V CC
V PFD (max)
V PFD (min)
V SO
ABE, AFE bit in Interrupt Register
AF bit in Flags Register
IRQ/FT
Back-up mode alarm waveforms
HIGH-Z
Figure 11 on page
19. The number of times pulses
Figure 10 on page
tREC
HIGH-Z
AI03254B
19).
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