adc08d1010diyb National Semiconductor Corporation, adc08d1010diyb Datasheet - Page 28

• Manufacturer Part Number: adc08d1010diyb
• Description: High Performance, Low Power, Dual 8-bit, 1 Gsps A/d Converter
• Manufacturer: National Semiconductor Corporation

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Bit 15:7
Bits 6:0
Addr: Bh (1011b)
Addr: Dh (1101b)
(MSB
(LSB
DEN ACP
D15
D15
D7
D7
1
)
)
Q-Channel Full-Scale Voltage Adjust
D14
D14
D6
D6
1
1
Full Scale Voltage Adjust Value. The input full-
scale voltage or gain of the I-Channel ADC is
adjusted linearly and monotonically with a 9 bit
data value. The adjustment range is ±20% of
the nominal 700 mV
0000 0000 0
1000 0000 0
1111 1111 1
For best performance, it is recommended that
the value in this field be limited to the range of
0110 0000 0b to 1110 0000 0b. i.e., limit the
amount of adjustment to ±15%. The remaining
±5% headroom allows for the ADC's own full
scale variation. A gain adjustment does not
require ADC re-calibration.
POR State: 1000 0000 0b (no adjustment)
Must be set to 1b
D13
D13
D5
D5
1
1
1
DES Enable
D12
D12
D4
D4
1
1
1
Adjust Value
D11
D11
560mV
700mV
840mV
D3
D3
1
1
1
P-P
differential value.
D10
D10
P-P
P-P
P-P
D2
D2
1
1
1
W only (0x3FFF)
W only (0x807F)
D9
D1
D9
D1
1
1
1
D8
D0
D8
D0
1
1
1
28
Bit 14
Bits 13:0
Bit 15
Bits 13:11 Coarse Adjust Magnitude. Each code value in
Bits 10:0 Must be set to 1b
Addr: Eh (1110b)
D15
Bit 15
Bit 14
D7
IS
1
ADS
D14
D6
1
DES Enable. Setting this bit to 1b enables the
Dual Edge Sampling mode. In this mode the
ADCs in this device are used to sample and
convert the same analog input in a time-
interleaved manner, accomplishing a
sampling rate of twice the input clock rate.
When this bit is set to 0b, the device operates
in the normal dual channel mode.
POR State: 0b
Automatic Clock Phase (ACP) Control. Setting
this bit to 1b enables the Automatic Clock
Phase Control. In this mode the DES Coarse
and Fine manual controls are disabled. A
phase detection circuit continually adjusts the
I and Q sampling edges to be 180 degrees out
of phase. When this bit is set to 0b, the sample
(input) clock delay between the I and Q
channels is set manually using the DES
Coarse and Fine Adjust registers. (See
Section 2.4.5 for important application
information) Using the ACP Control option
is recommended over the manual DES
settings.
POR State: 0b
Must be set to 1b
Input Select. When this bit is set to 0b the "I"
input is operated upon by both ADCs. When
this bit is set to 1b the "Q" input is operated on
by both ADCs.
POR State: 0b
Adjust Direction Select. When this bit is set to
0b, the programmed delays are applied to the
"I" channel sample clock while the "Q" channel
sample clock remains fixed. When this bit is
set to 1b, the programmed delays are applied
to the "Q" channel sample clock while the "I"
channel sample clock remains fixed.
POR State: 0b
this field delays either the "I" channel or the "Q"
channel sample clock (as determined by the
ADS bit) by approximately 20 picoseconds. A
value of 000b in this field causes zero
adjustment.
POR State: 000b
D13
D5
1
DES Coarse Adjust
CAM
D12
D4
1
D11
D3
1
D10
D2
1
1
W only (0x07FF)
D9
D1
1
1
D8
D0
1
1