adc08d1010diyb National Semiconductor Corporation, adc08d1010diyb Datasheet - Page 31

• Manufacturer Part Number: adc08d1010diyb
• Description: High Performance, Low Power, Dual 8-bit, 1 Gsps A/d Converter
• Manufacturer: National Semiconductor Corporation

2.2.1 Handling Single-Ended Input Signals
There is no provision for the ADC08D1010 to adequately pro-
cess single-ended input signals. The best way to handle
single-ended signals is to convert them to differential signals
before presenting them to the ADC. The easiest way to ac-
complish single-ended to differential signal conversion is with
an appropriate balun-connected transformer, as shown in
Figure 13.
The 100 Ohm external resistor placed across the output ter-
minals of the balun in parallel with the ADC08D1010's on-chip
100 Ohm resistor makes a 50 Ohms differential impedance
at the balun output. Or, 25 Ohms to virtual ground at each of
the balun output terminals.
Looking into the balun, the source sees the impedance of the
first coil in series with the impedance at the output of that coil.
Since the transformer has a 1:1 turns ratio, the impedance
across the first coil is exactly the same as that at the output
of the second coil, namely 25 Ohms to virtual ground. So, the
25 Ohms across the first coil in series with the 25 Ohms at its
output gives 50 Ohms total impedance to match the source.
2.2.2 Out Of Range (OR) Indication
When the conversion result is clipped the Out of Range output
is activated such that OR+ goes high and OR- goes low. This
output is active as long as accurate data on either or both of
the buses would be outside the range of 00h to FFh.
2.2.3 Full-Scale Input Range
As with all A/D Converters, the input range is determined by
the value of the ADC's reference voltage. The reference volt-
age of the ADC08D1010 is derived from an internal band-gap
reference. The FSR pin controls the effective reference volt-
age of the ADC08D1010 such that the differential full-scale
input range at the analog inputs is 870 mV
pin high, or is 650 mV
tained with FSR high, but better distortion and SFDR are
obtained with the FSR pin low.
2.3 THE CLOCK INPUTS
The ADC08D1010 has differential LVDS clock inputs, CLK+
and CLK-, which must be driven with an a.c. coupled, differ-
ential clock signal. Although the ADC08D1010 is tested and
its performance is guaranteed with a differential 1.0 GHz
clock, it typically will function well with input clock frequencies
indicated in the Electrical Characteristics Table. The clock in-
puts are internally terminated and biased. The input clock
signal must be capacitively coupled to the clock pins as indi-
cated in Figure 14.
Operation up to the sample rates indicated in the Electrical
Characteristics Table is typically possible if the maximum am-
bient temperatures indicated are not exceeded. Operating at
higher sample rates than indicated for the given ambient tem-
perature may result in reduced device reliability and product
conversion with a balun-connected transformer
FIGURE 13. Single-Ended to Differential signal
P-P
with FSR pin low. Best SNR is ob-
P-P
with the FSR
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lifetime. This is because of the higher power consumption and
die temperatures at high sample rates. Important also for re-
liability is proper thermal management . See Section 2.6.2.
The differential input clock line pair should have a character-
istic impedance of 100Ω and (when using a balun), be termi-
nated at the clock source in that (100Ω) characteristic
impedance. The input clock line should be as short and as
direct as possible. The ADC08D1010 clock input is internally
terminated with an untrimmed 100Ω resistor.
Insufficient input clock levels will result in poor dynamic per-
formance. Excessively high input clock levels could cause a
change in the analog input offset voltage. To avoid these
problems, keep the input clock level within the range specified
in the Electrical Characteristics Table.
The low and high times of the input clock signal can affect the
performance of any A/D Converter. The ADC08D1010 fea-
tures a duty cycle clock correction circuit which can maintain
performance over temperature even in DES mode. The ADC
will meet its performance specification if the input clock high
and low times are maintained within the range (20/80% ratio)
as specified in the Electrical Characteristics Table.
High speed, high performance ADCs such as the AD-
C08D1010 require a very stable input clock signal with mini-
mum phase noise or jitter. ADC jitter requirements are defined
by the ADC resolution (number of bits), maximum ADC input
frequency and the input signal amplitude relative to the ADC
input full scale range. The maximum jitter (the sum of the jitter
from all sources) allowed to prevent a jitter-induced reduction
in SNR is found to be
where t
V
full-scale range of the ADC, "N" is the ADC resolution in bits
and f
analog input.
Note that the maximum jitter described above is the arithmetic
sum of the jitter from all sources, including that in the ADC
input clock, that added by the system to the ADC input clock
and input signals and that added by the ADC itself. Since the
effective jitter added by the ADC is beyond user control, the
best the user can do is to keep the sum of the externally added
input clock jitter and the jitter added by the analog circuitry to
the analog signal to a minimum.
Input clock amplitudes above those specified in the Electrical
Characteristics Table may result in increased input offset volt-
age. This would cause the converter to produce an output
code other than the expected 127/128 when both input pins
are at the same potential.
FIGURE 14. Differential (LVDS) Input Clock Connection
IN(P-P)
IN
t
J(MAX)
is the maximum input frequency, in Hertz, to the ADC
J(MAX)
is the peak-to-peak analog input signal, V
= (V
is the rms total of all jitter sources in seconds,
IN(P-P)
/ V
INFSR
) x (1/(2
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(N+1)
x
π
x f
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INFSR
IN
))
is the