kad5514p Kenet Inc., kad5514p Datasheet - Page 16

• Manufacturer Part Number: kad5514p
• Description: 14-bit, 250/210/170/125msps Adc
• Manufacturer: Kenet Inc.

The calibration sequence is initiated on the rising
edge of RESETN, as shown in Figure 24. The over-
range output (OR) is set high once RESETN is pulled
low, and remains in that state until calibration is com-
plete. The OR output returns to normal operation at
that time, so it is important that the analog input be
within the converter’s full-scale range to observe the
transition. If the input is in an over-range condition
the OR pin will stay high, and it will not be possible to
detect the end of the calibration cycle.
W h i l e R E S E T N i s l o w , t h e o u t p u t c l o c k
(CLKOUTP/CLKOUTN) is set low. Normal operation of
the output clock resumes at the next input clock
edge (CLKP/CLKN) after RESETN is deasserted. At
250MSPS the nominal calibration time is 200ms, while
the maximum calibration time is 550ms.
User-Initiated Reset
Recalibration of the ADC can be initiated at any
time by driving the RESETN pin low for a minimum of
one clock cycle. An open-drain driver with a drive
strength of less than 0.5mA is recommended. As is the
case during power-on reset, the SDO, RESETN and
DNC pins must be in the proper state for the calibra-
tion to successfully execute.
The performance of the KAD5514P changes with
variations in temperature, supply voltage or sample
rate. The extent of these changes may necessitate
recalibration, depending on system performance
requirements. Best performance will be achieved by
recalibrating the ADC under the environmental con-
ditions at which it will operate.
A supply voltage variation of less than 100mV will
generally result in an SNR change of less than 0.5dBFS
and SFDR change of less than 3dBc.
In situations where the sample rate is not constant,
best results will be obtained if the device is calibrated
KAD5514P
Figure 24. Calibration Timing
Preliminary
at the highest sample rate. Reducing the sample rate
by less than 80MSPS will typically result in an SNR
change of less than 0.5dBFS and an SFDR change of
less than 3dBc.
Figures 25 and 26 show the effect of temperature on
SNR and SFDR performance without recalibration. In
each plot the ADC is calibrated at 25°C and tem-
perature is varied over the operating range without
recalibrating. The average change in SNR/SFDR is
shown, relative to the 25°C value.
Analog Input
A single fully differential input (VINP/VINN) connects
to the sample and hold amplifier (SHA) of each unit
ADC. The ideal full-scale input voltage is 1.45V, cen-
tered at the VCM voltage of 0.535V as shown in Fig-
ure 27.
Figure 26. SFDR Performance vs. Temperature after
Figure 25. SNR Performance vs. Temperature after
25°C Calibration
25°C Calibration
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