kad5512hp Kenet Inc., kad5512hp Datasheet
kad5512hp
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kad5512hp Summary of contents
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... Digital output data is presented in selectable LVDS or CMOS formats. The KAD5512HP is available in 72- and 48-contact QFN packages with an exposed paddle. Operating from a 1.8V supply, performance is specified over the full industrial temperature range (-40 to +85° ...
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... KAD5512HP Table of Contents Section Electrical Specifications DC Specifications AC Specifications Digital Specifications Absolute Maximum Ratings Timing Diagrams Switching Specifications Thermal Impedance ESD Pinout/Package Information Pin Descriptions—72QFN Pin Configuration—72QFN Pin Descriptions—48QFN Pin Configuration—48QFN Typical Performance Characteristics Theory of Operation Functional Description ...
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... LVDS 46 44 30MHz, -36 -36 200mVpp signal on AVDD 3mA LVDS 407 438 382 3mA LVDS 368 301 342 134 146 129 Maximum Conversion Rate (per speed KAD5512HP-17 KAD5512HP-12 Max Min Typ Max Min Typ Max 1.54 1.40 1.47 1.54 1.40 1.47 1.54 500 500 2.6 2 -10 ±2 10 -10 ± ...
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... 400MHz 10 995MHz 8 10MHz 70MHz 105MHz 230MHz 400MHz 995MHz 70MHz -91 170MHz -86 -12 950 KAD5512HP-17 KAD5512HP-12 Typ Max Min Typ Max Min ±0.6 -1.0 ±0.6 -1.0 ±1.3 ±1 170 125 68.0 68.4 67.8 68.3 67.6 66.2 68.0 66.7 67.6 68.0 67.7 68.0 67.5 68.0 67.0 65.7 67.4 66.2 67.9 68.3 11.0 11.0 10.9 11.0 10.8 10.6 10.9 10.7 11.0 11 ...
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... KAD5512HP Digital Specifications Parameter Inputs Input Current High (RESETN) Input Current Low (RESETN) Input Current High (OUTMODE, Input Current Low (OUTMODE, Input Capacitance LVDS Outputs Differential Output Voltage Output Offset Voltage Output Rise Time Output Fall Time CMOS Outputs Voltage Output High ...
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... KAD5512HP Absolute Maximum Ratings Parameter AVDD to AVSS OVDD to OVSS AVSS to OVSS Analog Inputs to AVSS Clock Inputs to AVSS Logic Input to AVSS Logic Inputs to OVSS Operating Temperature Storage Temperature Junction Temperature 1. Exposing the device to levels in excess of the maximum ratings may cause permanent damage. Exposure to maximum conditions for extended periods may affect device reliability ...
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... KAD5512HP Switching Specifications Parameter ADC Output Aperture Delay RMS Aperture Jitter Output Clock to Data Propagation Delay, LVDS Mode Output Clock to Data Propagation Delay, CMOS Mode Latency (Pipeline Delay) Over Voltage Recovery SPI Interface 1,2 SCLK Period SCLK Duty Cycle ( ...
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... KAD5512HP Pin Descriptions—72QFN Pin # LVDS [LVCMOS] Name 1, 6, 12, 19, 24, 71 AVDD 2-5, 13, 14, 17, 18, 28-31 DNC 7, 8, 11, 72 AVSS 9, 10 VINN, VINP 15 VCM 16 CLKDIV 20, 21 CLKP, CLKN 22 OUTMODE 23 NAPSLP 25 RESETN 26, 45, 55, 65 OVSS 27, 36, 56 OVDD 32, 33 D0N, D0P [NC, D0] 34, 35 D1N, D1P [NC, D1] ...
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... KAD5512HP Pin Configuration—72QFN AVDD 1 DNC 2 DNC 3 DNC 4 DNC 5 AVDD 6 AVSS 7 AVSS 8 VINN 9 VINP 10 AVSS 11 AVDD 12 DNC 13 DNC 14 VCM 15 CLKDIV 16 DNC 17 DNC 18 KAD5512 72 QFN Top View Not to Scale Figure 3. 72 QFN Pin Configuration 54 D8P 53 D8N 52 D7P 51 D7N 50 D6P 49 D6N 48 CLKOUTP 47 CLKOUTN ...
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... KAD5512HP Pin Descriptions—48QFN Pin # LVDS [LVCMOS] Name 1, 9, 13, 17, 47 AVDD 2-4, 11, 21, 22 DNC 5, 8, 12, 48 AVSS 6, 7 VINN, VINP 10 VCM 14, 15 CLKP, CLKN 16 NAPSLP 18 RESETN 19, 29, 42 OVSS 20, 37 OVDD 23, 24 D0N, D0P [NC, D0] 25, 26 D1N, D1P [NC, D1] 27, 28 D2N, D2P [NC, D2] ...
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... KAD5512HP Pin Configuration—48QFN AVDD DNC DNC DNC AVSS VINN VINP AVSS AVDD VCM DNC AVSS KAD5512 QFN Top View 11 Not to Scale 12 Figure 4. 48QFN Pin Configuration 36 D4P 35 D4N 34 D3P 33 D3N 32 CLKOUTP 31 CLKOUTN 30 RLVDS 29 OVSS 28 D2P 27 D2N 26 D1P ...
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... KAD5512HP Typical Performance Curves All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V + -1dBFS, f ° SFDR @ 125MSPS 85 SFDR @ 250MSPS 80 75 SNR @ 125MSPS SNR @ 250MSPS 200 400 INPUT FREQUENCY (MHz) Figure 5. SNR & SFDR vs. f ...
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... KAD5512HP Typical Performance Curves All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V + -1dBFS, f ° 450 SDR 400 350 300 250 200 150 100 100 130 SAMPLE RATE (MSPS) Figure 11. Power vs. f ...
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... KAD5512HP Typical Performance Curves All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V + -1dBFS, f ° Ain = -1.0 dBFS -20 SNR = 66.6 dBFS SFDR = 79.8 dBc SINAD = 66.2 dBFS -40 -60 -80 -100 -120 FREQUENCY (MHz) Figure 17. Single-Tone Spectrum @ 137 MHz ...
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... KAD5512HP Functional Description The KAD5512HP is based upon a 12-bit, 250MSPS A/D converter core that utilizes a pipelined successive approximation architecture (Figure 23). The input voltage is captured by a Sample-Hold Amplifier (SHA) and converted to a unit of charge. Proprietary charge-domain techniques are used to successively compare the input to a series of reference charges. ...
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... SDO, RESETN and DNC pins must be in the proper state for the calibra- tion to successfully execute. The performance of the KAD5512HP changes with variations in temperature, supply voltage or sample rate. The extent of these changes may necessitate recalibration, depending on system performance requirements ...
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... VCM. The value of the shunt resistor should be determined based on the desired load impedance. The differential input resistance of the KAD5512HP is 500Ω. The SHA design uses a switched capacitor input stage (see Figure 43), which creates current spikes when the sampling capacitance is reconnected to the input voltage ...
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... KAD5512HP CLKDIV Pin Divide Ratio AVSS Float AVDD Table 1. CLKDIV Pin Settings The clock divider can also be controlled through the SPI port, which overrides the CLKDIV pin setting. De- tails on this are contained in the Serial Peripheral In- terface section. A delay-locked loop (DLL) generates internal clock signals for various stages within the charge pipeline ...
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... The OR bit is updated at the sample rate. Power Dissipation The power dissipated by the KAD5512HP is primarily dependent on the sample rate and the output modes: LVDS vs. CMOS and DDR vs. SDR. There is a static bias in the analog supply, while the remaining power dissipation is linearly related to the sample rate ...
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... KAD5512HP Figure 34. Gray Code to Binary Conversion Mapping of the input voltage to the various data for- mats is shown in Table 5. Input Voltage –Full Scale 000000000000 –Full Scale 000000000001 + 1LSB Mid–Scale 100000000000 +Full Scale 111111111110 – 1LSB +Full Scale 111111111111 Table 5. Input Voltage to Output Code Mapping ...
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... The SPI port operates in a half duplex master/slave configuration, with the KAD5512HP functioning as a slave. Multiple slave devices can interface to a single master in four-wire mode only, since the SDIO output of an unaddressed device is asserted in three wire mode ...
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... KAD5512HP and LSB-first modes, respectively. In MSB-first mode the address is incremented for multi-byte transfers, while in LSB-first mode it’s decremented. In the default mode the MSB is R/W, which deter- mines if the data read (active high) or writ- ten. The next two bits, W1 and W0, determine the number of data bytes to be read or written (see Ta- ble 6) ...
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... KAD5512HP The default value of each register will be the result of the self-calibration after initial power-up register incremented or decremented, the user should first read the register value then write the incremented or decremented value back to the same register. Parameter 0x20[7:0] Coarse Offset ...
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... Address 0x73: output_mode_A The output_mode_A register controls the physical out- put format of the data, as well as the logical coding. The KAD5512HP can present output data in two physi- cal formats: LVDS or LVCMOS. Additionally, the drive strength in LVDS mode can be set high (3mA) or low (2mA) ...
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... XOR result to the register. Device Test The KAD5512HP can produce preset or user defined patterns on the digital outputs to facilitate in-situ test- ing. A static word can be placed on the output bus, or two different words can alternate. In the alternate ...
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... KAD5512HP SPI Memory Map Addr (Hex) Parameter Name Bit 7 (MSB) 00 port_config SDO Active LSB First 01 reserved 02 burst_end 03-07 reserved 08 chip_id 09 chip_version 10 device_index_A 11-1F reserved 20 offset_coarse 21 offset_fine 22 gain_coarse 23 gain_medium 24 gain_fine 25 modes 26-5F reserved 60-6F reserved 70 reserved 71 phase_slip 72 clock_divide 73 output_mode_A Output Mode [2:0] 000=Pin Control 001=LVDS 2mA 010=LVDS 3mA ...
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... KAD5512HP Equivalent Circuits Figure 43. Analog Inputs Figure 44. Clock Inputs Figure 45. Tri-Level Digital Inputs Figure 46. Digital Inputs Figure 47. LVDS Outputs Figure 48. CMOS Outputs Figure 49. VCM_OUT Output Layout Considerations Split Ground and Power Planes Data converters operating at high sampling frequen- cies require extra care in PC board layout. Many complex board designs benefit from isolating the analog and digital sections ...
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... KAD5512HP Exposed Paddle The exposed paddle must be electrically connected to analog ground (AVSS) and should be connected to a large copper plane using numerous vias for opti- mal thermal performance. Bypass and Filtering Bulk capacitors should have low equivalent series re- sistance. Tantalum is a good choice. For best per- formance, keep ceramic bypass capacitors very close to device pins ...
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... KAD5512HP Outline Dimensions—72QFN Figure 50. 72QFN Dimensions Page 29 ...
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... KAD5512HP Outline Dimensions—48QFN Figure 51. 48QFN Dimensions Page 30 ...
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... KAD5512HP Ordering Guide The KAD5512HP is compliant with EU directive 2002/95/EC regarding the Restriction of Hazardous Sub- stances (RoHS). Contact Kenet for a materials declaration for this product. Model KAD5512HP-25Q72 KAD5512HP-21Q72 KAD5512HP-17Q72 KAD5512HP-12Q72 KAD5512HP-25Q48 KAD5512HP-21Q48 KAD5512HP-17Q48 KAD5512HP-12Q48 Revision History 30-Jul-08: Rev 1 Initial Release of Production Datasheet Information provided by Kenet, Inc ...