kad5610p Kenet Inc., kad5610p Datasheet
kad5610p
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kad5610p Summary of contents
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... Digital output data is presented in selectable LVDS or CMOS formats. The KAD5610P is available in a 72- contact QFN package with an exposed paddle. Performance is specified over the full industrial temperature range (-40 to +85°C). ...
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... KAD5610P Table of Contents Section Electrical Specifications DC Specifications AC Specifications Digital Specifications Timing Diagrams Switching Specifications Absolute Maximum Ratings Thermal Impedance ESD Pinout/Package Information Pin Descriptions Pin Configuration Typical Performance Characteristics Theory of Operation Functional Description Power-On Calibration User-Initiated Reset Analog Input Clock Input ...
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... Conditions Min Typ Max Min Differential 1.38 1.45 1.59 1.38 Differential 1000 Differential 4 Full Temp 90 ±1.5 ±0.6 0.535 1.7 1.8 1.9 1.7 1.7 1.8 1.9 1.7 157 TBD 65.0 TBD -53 400 TBD 40 TBD 10 TBD KAD5610P-17 KAD5610P-12 Typ Max Min Typ Max Min 1.45 1.59 1.38 1.45 1.59 1.38 1000 1000 1000 ±1.5 ±1.5 ±0.6 ±0.6 0.535 0.535 0.535 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 1.7 ...
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... TBD TBD 170MHz TBD 10MHz 124MHz 170MHz TBD IN 10 -12 1.3 KAD5610P-17 KAD5610P-12 Typ Max Min Typ Max Min TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 170 125 TBD TBD TBD TBD TBD TBD TBD ...
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... KAD5610P Digital Specifications Parameter Inputs Input Current High (RESETN) Input Current Low (RESETN) Input Current High (OUTMODE, NAP/SLP, CLKDIV, OUTFMT ) Input Current Low (OUTMODE, NAP/SLP, CLKDIV, OUTFMT ) Input Capacitance LVDS Outputs Differential Output Voltage Output Offset Voltage Output Rise Time Output Fall Time ...
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... KAD5610P Switching Specifications Parameter ADC Aperture Delay RMS Aperture Jitter Input Clock to Output Clock Propagation Delay Input Clock to Data Propagation Delay Output Clock to Data Propagation Delay Latency (Pipeline Delay) Over Voltage Recovery Absolute Maximum Ratings Parameter AVDD to AVSS OVDD to OVSS AVSS to OVSS ...
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... KAD5610P Thermal Impedance Parameter Junction to Paddle 2 Junction to Case 2 Junction to Ambient 2 2. Paddle soldered to ground plane. ESD Electrostatic charge accumulates on humans, tools and equipment and may discharge through any metallic package contacts (pins, balls, exposed paddle, etc integrated circuit. Industry-standard protection techniques have been utilized in the design of this prod- uct ...
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... KAD5610P Pin Descriptions Pin # LVDS [LVCMOS] Name 1, 6, 19, 24, 71 AVDD 2-5, 17, 18, 28-35 DNC 7, 10-12, 72 AVSS 8, 9 BINP, BINN 13, 14 AINN, AINP 15 VCM 16 CLKDIV 20, 21 CLKP, CLKN 22 OUTMODE 23 NAPSLP 25 RESETN 26, 45, 55, 65 OVSS 27, 36, 56 OVDD 37, 38 D0N, D0P [NC, D0] 39, 40 D1N, D1P [NC, D1] ...
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... KAD5610P Pin Configuration AVDD 1 DNC 2 DNC 3 DNC 4 DNC 5 AVDD 6 AVSS 7 BINP 8 BINN 9 AVSS 10 AVSS 11 AVSS 12 AINN 13 AINP 14 VCM 15 CLKDIV 16 DNC 17 DNC 18 Rev 0.5.1 Preliminary KAD5610 72 QFN Top View Not to Scale Figure 3. Pin Configuration 54 D6P 53 D6N 52 D5P 51 D5N 50 D4P 49 D4N 48 CLKOUTP 47 CLKOUTN 46 RLVDS ...
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... KAD5610P Typical Performance Curves 90 85 SFDR SNRFS 50 0 200 400 INPUT FREQUENCY (MHz) Figure 4. SNR & SFDR vs. f TBD Figure 6. SNR & SFDR vs. A TBD Figure 8. SNR & SFDR vs. f Rev 0.5.1 Preliminary 600 800 1000 IN IN SAMPLE TBD Figure 5. HD2 & ...
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... KAD5610P Typical Performance Curves TBD Figure 10. Power vs. f TBD Figure 12. Integral Nonlinearity TBD Figure 14. Noise Histogram Rev 0.5.1 Preliminary SAMPLE Figure 15. Single Tone Spectrum @ 10 MHz TBD Figure 11. Differential Nonlinearity TBD Figure 13. SNR & SFDR vs. VCM TBD Page 11 ...
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... KAD5610P Typical Performance Curves TBD Figure 16. Single Tone Spectrum @ 70 MHz TBD Figure 18. Single Tone Spectrum @ 240 MHz TBD Figure 20. Two-Tone Spectrum @ 10 MHz Rev 0.5.1 Preliminary TBD Figure 17. Single Tone Spectrum @ 140 MHz TBD Figure 19. Single Tone Spectrum @ 500 MHz TBD Figure 21. Two-Tone Spectrum @ 70 MHz ...
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... KAD5610P Typical Performance Curves TBD Figure 22. Two-Tone Spectrum @ 140 MHz TBD Figure 24. Two-Tone Spectrum @ 500 MHz TBD Figure 26. SNR & SFDR vs. Power Supply Voltage Rev 0.5.1 Preliminary TBD Figure 23. Two-Tone Spectrum @ 240 MHz TBD Figure 25. SNR & SFDR vs. Temperature Page 13 ...
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... KAD5610P Functional Description The KAD5610P is based upon a 10-bit, 250MSPS A/D converter core that utilizes a pipelined successive approximation architecture (Figure 27). The input voltage is captured by a Sample-Hold Amplifier (SHA) and converted to a unit of charge. Proprietary charge domain techniques are used to successively compare the input to a series of reference charges. ...
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... VCM. The value of the shunt resistor should be determined based on the desired load impedance. The differen- tial input resistance of the KAD5610P is 1000Ω. The SHA design uses a switched capacitor input stage, which creates charge kick-back when the sampling capacitance is reconnected to the input voltage ...
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... KAD5610P Figure 32. Differential Amplifier Input A differential amplifier, as shown in Figure 32, can be used in applications that require dc-coupling. In this configuration the amplifier will typically dominate the achievable SNR and distortion performance. Clock Input The clock input circuit is a differential pair (see Figure 47). Driving these inputs with a high level (up to 1.8V on each input) sine or square wave will provide the lowest jitter performance ...
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... A 10kΩ, 1% resistor must be connected from the RLVDS pin to OVSS. Power Dissipation The power dissipated by the KAD5610P is primarily dependent on the sample rate, but is also related to the input signal in CMOS output mode. There is a static bias in the analog supply, while the remaining power dissipation is linearly related to the sample rate ...
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... KAD5610P The power down mode can also be controlled through the SPI port, which overrides the NAPSLP pin setting. Details on this are contained in the Serial Pe- ripheral Interface section. This is an indexed function when controlled from the SPI, but a global function when driven from the pin. ...
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... SPI Physical Interface The SPI port operates in a half or full duplex mas- ter/slave configuration, with the KAD5610P function- ing as a slave. Multiple slave devices can interface to a single master. The chip-select bar (CSB) pin deter- mines when a slave device is being addressed. Multi- ...
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... KAD5610P [W1:W0] Bytes Transferred Table 6. Byte Transfer Selection Figures 42 and 43 illustrate the timing relationships for 2-byte and N-byte transfers, respectively. The opera- tion for a 3-byte transfer can be inferred from these diagrams. SPI Configuration Address 0x00: chip_port_config Bit ordering and SPI reset are controlled by this regis- ter ...
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... KAD5610P Address 0x02: burst_end If a series of sequential registers are to be set, burst mode can improve throughput by eliminating redun- dant addressing. In 3-wire SPI mode the burst is ended by pulling the CSB pin high. If the device is operated in 2-wire mode the CSB pin is not available. ...
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... Address 0x73: output_mode_A -6.5ps The output_mode_A register controls the physical 0.0ps output format of the data, as well as the logical cod- ing. The KAD5610P can present output data in two +6.5ps physical formats: LVDS or LVCMOS. Additionally, the 51fs drive strength in LVDS mode can be set high (3mA) or low (2mA) ...
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... KAD5610P Value 000 001 010 100 Table 13. Output Mode Control Value 000 001 Two’s Complement 010 100 Table 14. Output Format Control Address 0x74: output_mode_B Address 0x75: config_status Bit 6 DLL Range This bit sets the DLL operating range to fast (TBD2MSPS to 250MSPS) or slow (40 to TBD1MSPS) ...
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... KAD5610P SPI Memory Map Addr (Hex) Parameter Name Bit 7 (MSB) 00 port_config SDO Active LSB First 01 reserved 02 burst_end 03-07 reserved 08 chip_id 09 chip_version 10 device_index_A 11-1F reserved 20 offset_coarse 21 offset_fine 22 gain_coarse 23 gain_medium 24 gain_fine 25 modes 26-5F reserved 60-6F reserved 70 skew_diff 71 phase_slip 72 clock_divide 73 output_mode_A Output Mode [2:0] 000=Pin Control 001=LVDS 2mA 010=LVDS 3mA ...
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... KAD5610P Equivalent Circuits Figure 46. Analog Inputs AVDD CLKP AVDD 11kΩ 18kΩ 18kΩ AVDD 11kΩ CLKN Figure 47. Clock Inputs Figure 48. Tri-Level Digital Inputs Figure 49. Digital Inputs Rev 0.5.1 Preliminary AVDD To Charge Pipeline Layout Considerations Split Ground and Power Planes Data converters operating at high sampling frequen- cies require extra care in PC board layout ...
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... KAD5610P Exposed Paddle The exposed paddle must be electrically connected to analog ground (AVSS) and should be connected to a large copper plane using numerous vias for opti- mal thermal performance. Bypass and Filtering Bulk capacitors should have low equivalent series re- sistance. Tantalum is a good choice. For best per- formance, keep ceramic bypass capacitors very close to device pins ...
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... KAD5610P Spurious-Free-Dynamic Range (SFDR) is the ratio of the RMS signal amplitude to the RMS value of the peak spurious spectral component. The peak spuri- ous spectral component may or may not be a har- monic. Two-Tone SFDR is the ratio of the RMS value of the lowest power input tone to the RMS value of the peak spurious component, which may or may not be an IMD product ...
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... KAD5610P Ordering Guide The KAD5610P is compliant with EU directive 2002/95/EC regarding the Restriction of Hazardous Sub- RoHS stances (RoHS). Contact Kenet for a materials declaration for this product. Model KAD5610P-25Q72 KAD5610P-21Q72 KAD5610P-17Q72 KAD5610P-12Q72 Revision History 14-May-07: Rev 0.1 Updated to new format 21-Jun-07: Rev 0.2 Errata Updated 13-Aug-07: Rev 0 ...