kad5510p-50 Kenet Inc., kad5510p-50 Datasheet - Page 22

• Manufacturer Part Number: kad5510p-50
• Description: 10-bit, 500msps A/d Converter
• Manufacturer: Kenet Inc.

Address 0x25: modes
Two distinct reduced power modes can be selected.
By default, the tri-level NAPSLP pin can select normal
operation, nap or sleep modes (refer to Nap/Sleep
section). This functionality can be overridden and
controlled through the SPI. This is an indexed function
when controlled from the SPI, but a global function
when driven from the pin. This register is not changed
by a Soft Reset.
Global DUT Configuration/Control
Address 0x70: skew_diff
The value in the skew_diff register adjusts the timing
skew between the two ADCs cores. The nominal
range and resolution of this adjustment are given in
Table 11. The default value of this register after
power-up is 00h.
Rev 0.5.1
KAD5510P-50
Table 9. Medium and Fine Gain Adjustments
Nominal Step Size
–Full Scale (0x80)
Mid–Scale (0x00)
+Full Scale (0x7F)
Parameter
Table 11. Differential Skew Adjustment
Steps
Nominal Step Size
+Full Scale (0x07)
–Full Scale (0x08)
Mid–Scale (0x00)
Table 10. Power Down Control
Parameter
Value
Steps
000
001
010
100
Medium Gain
0x23[7:0]
+10.48%
0.0825%
-10.56%
0.0%
256
Differential Skew
Power Down Mode
Normal Operation
0x70[7:0]
+6.5ps
Sleep Mode
-6.5ps
0.0ps
Nap Mode
Pin Control
51fs
0x25[2:0]
256
Fine Gain
0x24[7:0]
0.00825%
+1.05%
-1.06%
0.0%
256
Address 0x71: phase_slip
When using a clock divider, it’s not possible to deter-
mine the synchronization of the incoming and di-
vided clock phases. This is particularly important
when multiple ADCs are used in a time-interleaved
system. The phase slip feature allows the rising edge
of the divided clock to be advanced by one input
clock cycle, as shown in Figure 44.
Address 0x72: clock_divide
The KAD5510P has a selectable clock divider that
can be set to divide by four, two or one (no division).
By default, the tri-level CLKDIV pin selects the divisor
(refer to Clock Input section). This functionality can
be overridden and controlled through the SPI, as
shown in Table 12. This register is not changed by a
Soft Reset.
Address 0x73: output_mode_A
The output_mode_A register controls the physical
output format of the data, as well as the logical cod-
ing. The KAD5510P can present output data in two
physical formats: LVDS or LVCMOS. Additionally, the
drive strength in LVDS mode can be set high (3mA) or
low (2mA). By default, the tri-level OUTMODE pin se-
lects the mode and drive level (refer to Digital Out-
puts section). This functionality can be overridden
and controlled through the SPI, as shown in Table 13.
Data can be coded in three possible formats: two’s
complement, Gray code or offset binary. By default,
the tri-level OUTFMT pin selects the data format (refer
to Data Format section). This functionality can be
Table 12. Clock Divider Selection
Value
000
001
010
100
Figure 44. Phase Slip
Clock Divider
Divide by 1
Divide by 2
Divide by 4
Pin Control
0x72[2:0]
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