kad5612p Kenet Inc., kad5612p Datasheet - Page 21

no-image

kad5612p

Manufacturer Part Number
kad5612p
Description
Dual 12-bit, 250/210/170/125msps A/d Converter
Manufacturer
Kenet Inc.
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
kad5612p-12Q72
Manufacturer:
Intersil
Quantity:
1 400
Part Number:
kad5612p-17Q72
Manufacturer:
Intersil
Quantity:
1 400
Part Number:
kad5612p-21Q72
Manufacturer:
Intersil
Quantity:
1 400
Part Number:
kad5612p-25Q72
Manufacturer:
Intersil
Quantity:
27
Part Number:
kad5612p-25Q72
Manufacturer:
Intersil
Quantity:
1 400
The default value of each register will be the result of
the self-calibration after initial power-up. If a register is
to be incremented or decremented, the user should
first read the register value then write the incre-
mented or decremented value back to the same
register.
Address 0x22: gain_coarse
Address 0x23: gain_medium
Address 0x24: gain_fine
Gain of each ADC core can be adjusted in coarse,
medium and fine steps. Coarse gain is a 4-bit adjust-
ment while medium and fine are 8-bit.
The default value of each register will be the result of
the self-calibration after initial power-up. If a register is
to be incremented or decremented, the user should
first read the register value then write the incre-
mented or decremented value back to the same
register.
KAD5612P
Nominal Step Size
–Full Scale (0x00)
Mid–Scale (0x80)
+Full Scale (0xFF)
Parameter
Steps
Table 8. Coarse Gain Adjustment
Table 7. Offset Adjustments
0x22[3:0]
1100
1000
0100
0000
0001
0010
0011
+133LSB (+47mV)
1.04LSB (0.37mV)
-133LSB (-47mV)
Coarse Offset
0.0LSB (0.0mV)
0x20[7:0]
255
Nominal Coarse
Gain Adjust
-1.4%
-2.8%
-4.2%
4.2%
2.8%
1.4%
0.0%
0.04LSB (0.014mV)
+5LSB (+1.75mV)
-5LSB (-1.75mV)
Fine Offset
0x21[7:0]
0.0LSB
255
Address 0x25: modes
Two distinct reduced power modes can be selected.
By default, the tri-level NAPSLP pin can select normal
operation, nap or sleep modes (refer to Nap/Sleep
section). This functionality can be overridden and
controlled through the SPI. This is an indexed function
when controlled from the SPI, but a global function
when driven from the pin. This register is not changed
by a Soft Reset.
Global Device Configuration/Control
Address 0x70: skew_diff
The value in the skew_diff register adjusts the timing
skew between the two ADCs cores. The nominal
range and resolution of this adjustment are given in
Table 11. The default value of this register after
power-up is 00h.
Table 9. Medium and Fine Gain Adjustments
Nominal Step Size
Mid–Scale (0x80)
–Full Scale (0x00)
+Full Scale (0xFF)
Parameter
Table 11. Differential Skew Adjustment
Steps
Nominal Step Size
–Full Scale (0x00)
Mid–Scale (0x80)
+Full Scale (0xFF)
Table 10. Power Down Control
Parameter
Value
Steps
000
001
010
100
Medium Gain
0x23[7:0]
0.016%
0.0%
+2%
256
-2%
Differential Skew
Power Down Mode
Normal Operation
0x70[7:0]
+6.5ps
Sleep Mode
-6.5ps
0.0ps
Pin Control
Nap Mode
51fs
0x25[2:0]
256
Fine Gain
0x24[7:0]
0.0016%
+0.2%
-0.2%
0.0%
256
Page 21

Related parts for kad5612p