kad5610p Kenet Inc., kad5610p Datasheet - Page 14

• Manufacturer Part Number: kad5610p
• Description: Dual 10-bit, 250/210/170/125msps A/d Converter
• Manufacturer: Kenet Inc.

Functional Description
The KAD5610P is based upon a 10-bit, 250MSPS A/D
converter core that utilizes a pipelined successive
approximation architecture (Figure 27). The input
voltage is captured by a Sample-Hold Amplifier (SHA)
and converted to a unit of charge. Proprietary
charge domain techniques are used to successively
compare the input to a series of reference charges.
Decisions made during the successive approximation
operations determine the digital code for each input
value. The converter pipeline requires six samples to
produce a result. Digital error correction is also ap-
plied, resulting in a total latency of seven and a half
clock cycles. This is evident to the user as a latency
between the start of a conversion and the data be-
ing available on the digital outputs.
The device contains two A/D converter cores with
carefully matched transfer characteristics. At start-
up, each core performs a self-calibration to minimize
gain and offset errors. The reset pin (RESETN) is initially
set high at power-up and will remain in that state until
the calibration is complete. The clock frequency
should remain fixed during this time, and no SPI com-
munications should be attempted. Recalibration can
be initiated via the SPI port at any time after the initial
self-calibration.
Rev 0.5.1 Preliminary
KAD5610P
Figure 27. ADC Core Block Diagram
Power-On Calibration
At start-up, the core performs a self-calibration to
minimize gain and offset errors. An internal power-on-
reset (POR) circuit detects the supply voltage ramps
and initiates the calibration when the analog and
digital supply voltages are above a threshold. The
following conditions must be adhered to for the
power-on calibration to execute successfully:
A user-initiated reset can subsequently be invoked in
the event that the above conditions cannot be met
at power-up.
The SDO pin requires an external 4.7kΩ pull-up to
OVDD. If the SDO pin is pulled low externally during
power-up, calibration will not be executed properly.
After the power supply has stabilized the internal POR
releases RESETN and an internal pull-up pulls it high,
which starts the calibration sequence. The RESETN pin
should be connected to an open-drain driver with a
drive strength of less than 0.5mA.
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A frequency-stable conversion clock must be
applied to the CLKP/CLKN pins
DNC pins (especially 3, 4 and 18) must not be
pulled up or down
SDO (pin 66) must be high
RESETN (pin 25) must begin low
SPI communications must not be attempted
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