pca9506dgg NXP Semiconductors, pca9506dgg Datasheet - Page 11

• Manufacturer Part Number: pca9506dgg
• Description: Pca9505/pca9506 40-bit I2c-bus I/o Port With Reset, Oe And Int
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 5.
Legend: * default value.
Table 6.
Legend: * default value.
PCA9505_9506_3
Product data sheet
Address
08h
09h
0Ah
0Bh
0Ch
Address
10h
11h
12h
13h
14h
OP0 to OP4 - Output Port registers (address 08h to 0Ch) bit description
PI0 to PI4 - Polarity Inversion registers (address 10h to 14h) bit description
Register
OP0
OP1
OP2
OP3
OP4
Register
PI0
PI1
PI2
PI3
PI4
7.3.2 OP0 to OP4 - Output Port registers
7.3.3 PI0 to PI4 - Polarity Inversion registers
These registers reflect the outgoing logic levels of the pins defined as outputs by the
I/O Configuration register. Bit values in these registers have no effect on pins defined as
inputs. In turn, reads from these registers reflect the values that are in the flip-flops
controlling the output selection, not the actual pin values.
Where ‘x’ refers to the bank number (0 to 4); ‘y’ refers to the bit number (0 to 7).
These registers allow inversion of the polarity of the corresponding Input Port register.
Where ‘x’ refers to the bank number (0 to 4); ‘y’ refers to the bit number (0 to 7).
Ox[y] = 0: IOx_y = 0 if IOx_y defined as output (Cx[y] in IOC register = 0).
Ox[y] = 1: IOx_y = 1 if IOx_y defined as output (Cx[y] in IOC register = 0).
Px[y] = 0: The corresponding Input Port register data polarity is retained.
Px[y] = 1: The corresponding Input Port register data polarity is inverted.
Bit
7 to 0
7 to 0
7 to 0
7 to 0
7 to 0
Bit
7 to 0
7 to 0
7 to 0
7 to 0
7 to 0
Symbol
O0[7:0]
O1[7:0]
O2[7:0]
O3[7:0]
O4[7:0]
Symbol
P0[7:0]
P1[7:0]
P2[7:0]
P3[7:0]
P4[7:0]
Rev. 03 — 6 June 2007
Access
R/W
R/W
R/W
R/W
R/W
Access
R/W
R/W
R/W
R/W
R/W
40-bit I
Value
0000 0000*
0000 0000*
0000 0000*
0000 0000*
0000 0000*
Value
0000 0000*
0000 0000*
0000 0000*
0000 0000*
0000 0000*
2
C-bus I/O port with RESET, OE and INT
Description
Output Port register bank 0
Output Port register bank 1
Output Port register bank 2
Output Port register bank 3
Output Port register bank 4
Description
Polarity Inversion register bank 0
Polarity Inversion register bank 1
Polarity Inversion register bank 2
Polarity Inversion register bank 3
Polarity Inversion register bank 4
PCA9505/06
© NXP B.V. 2007. All rights reserved.
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