pca9506dgg NXP Semiconductors, pca9506dgg Datasheet - Page 8

• Manufacturer Part Number: pca9506dgg
• Description: Pca9505/pca9506 40-bit I2c-bus I/o Port With Reset, Oe And Int
• Manufacturer: NXP Semiconductors

NXP Semiconductors
PCA9505_9506_3
Product data sheet
The lowest 6 bits are used as a pointer to determine which register will be accessed. The
registers are:
If the Auto-Increment flag is set (AI = 1), the 3 least significant bits are automatically
incremented after a read or write. This allows the user to program and/or read the
5 register banks sequentially.
If more than 5 bytes of data are written and AI = 1, previous data in the selected registers
will be overwritten. Reserved registers are skipped and not accessed (refer to
If the Auto-Increment flag is cleared (AI = 0), the 3 least significant bits are not
incremented after data is read or written. During a read operation, the same register bank
is read each time. During a write operation, data is written to the same register bank each
time.
Only a Command register code with the 5 least significant bits equal to the 25 allowable
values as defined in
be accessed for proper device functionality. At power-up, this register defaults to 0x80,
with the AI bit set to logic 1, and the lowest 7 bits set to logic 0.
During a write operation, the PCA9505/06 will acknowledge a byte sent to OPx, PIx, and
IOCx and MSKx registers, but will not acknowledge a byte sent to the IPx registers since
these are read-only registers.
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•
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•
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IP: Input Port registers (5 registers)
OP: Output Port registers (5 registers)
PI: Polarity Inversion registers (5 registers)
IOC: I/O Configuration registers (5 registers)
MSK: Mask interrupt registers (5 registers)
Table 3
Rev. 03 — 6 June 2007
are valid. Reserved or undefined command codes must not
40-bit I
2
C-bus I/O port with RESET, OE and INT
PCA9505/06
© NXP B.V. 2007. All rights reserved.
Table
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3).