pca9506dgg NXP Semiconductors, pca9506dgg Datasheet - Page 14

• Manufacturer Part Number: pca9506dgg
• Description: Pca9505/pca9506 40-bit I2c-bus I/o Port With Reset, Oe And Int
• Manufacturer: NXP Semiconductors

NXP Semiconductors
8. Characteristics of the I
PCA9505_9506_3
Product data sheet
8.1.1 START and STOP conditions
8.1 Bit transfer
8.2 System configuration
The I
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see
A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘master' and the devices which are controlled by
the master are the ‘slaves' (see
Fig 7. Bit transfer
Fig 8. Definition of START and STOP conditions
2
C-bus is for 2-way, 2-line communication between different ICs or modules. The two
SDA
SCL
START condition
2
SDA
SCL
Figure
C-bus
S
Rev. 03 — 6 June 2007
8).
Figure
data valid
data line
stable;
9).
40-bit I
Figure
allowed
change
of data
2
C-bus I/O port with RESET, OE and INT
7).
STOP condition
PCA9505/06
mba607
P
© NXP B.V. 2007. All rights reserved.
mba608
SDA
SCL
14 of 31