pca9665 NXP Semiconductors, pca9665 Datasheet - Page 52

• Manufacturer Part Number: pca9665
• Description: Fm+ Parallel Bus To I2c-bus Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 42.
PCA9665_2
Product data sheet
Operation performed
Master Transmitter Buffered mode
After START condition
After Slave Address Sent + ACK bit received and interrupt received
After Slave Address Sent + NACK bit received
After Slave Address Sent + ‘n’ data bytes sent, ACK bit received, both
address and ‘n’ data
After Slave Address Sent + ‘n’ data bytes sent, last byte
After STOP
After losing arbitration in Slave Address + W and addressed as slave
After losing arbitration in slave address + W and not addressed as slave 0
After losing arbitration in data at n
Master Receiver Buffered mode
After START condition
After Slave Address Sent + ACK bit received
After Slave Address Sent + NACK bit received
After Slave Address Sent + ‘n’ data bytes received, ACK bit received for
address and ACK bit returned for ‘n’ data bytes
After Slave Address Sent + ‘n’ data bytes received, NACK bit returned
for the last byte
After STOP
After losing arbitration in Slave Address + R bit and addressed as slave 0
After losing arbitration in slave address + R and not addressed as slave 0
After losing arbitration in ACK of n
Slave Receiver Buffered mode (regular slave mode and General Call response
After Slave Address + W and ACK bit returned for slave address (both in
regular mode and when PCA9665 loses arbitration and is addressed as
slave)
After receiving ‘n’ bytes, ACK bit returned for the ‘n’ bytes
After receiving ‘n’ bytes, NACK bit returned for the last byte
Slave Transmitter Buffered mode
After Slave Address + R and ACK bit returned for slave address (both in
regular mode and when PCA9665 loses arbitration and is addressed as
slave)
After ‘n’ data bytes transmitted and ACK bit received for ‘n’ bytes
After ‘n’ data bytes transmitted and NACK bit received for the last byte
I2CCOUNT register value based on the performed operation
In Buffered Receiver mode, when an interrupt is generated and SI is set to 1 (after a
STOP command or a buffer full condition), the buffer pointer is reset and points at the first
received data byte. Reading the I2CCOUNT register then indicates the number of bytes
that have been sent or received (BC[6:0]). Reading of the data from I2CDAT buffer can
then be initiated starting with the first received byte.
th
th
byte
byte
Rev. 02 — 7 December 2006
I2CCOUNT register value
don’t care
1
1
n + 1
n + 1
don’t care
0
n (if there was no interrupt after slave address was
sent)
n
was sent)
don't care
don't care (because no interrupt received here)
1
n
n
don't care
n
0
n
n
0
n
n
1 (if there was an interrupt after slave address
Fm+ parallel bus to I
PCA9665
© NXP B.V. 2006. All rights reserved.
2
C-bus controller
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