pca9691 NXP Semiconductors, pca9691 Datasheet - Page 13

• Manufacturer Part Number: pca9691
• Description: 8-bit A/d And D/a Converter
• Manufacturer: NXP Semiconductors

NXP Semiconductors
PCA9691_1
Product data sheet
7.7.1 Bit transfer
7.7.2 Start and stop conditions
7.7.3 System configuration
7.7 Characteristics of the I
It is recommended that if the I
frequency by half (see the definition of the control byte in
If pin EXT is connected to V
state allowing to feed an external clock signal to the OSC input. The frequency of the
external clock must be in the specified range.
The I
The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines are
connected to a positive supply via a pull-up resistor. Data transfer is initiated only when
the bus is not busy.
One data bit is transferred during each clock pulse. The data on the SDA line remains
stable during the HIGH period of the clock pulse as changes in the data line at this time
are interpreted as control signals (see
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line, while the clock is HIGH, is defined as the start condition [S]. A
LOW-to-HIGH transition of the data line while the clock is HIGH, is defined as the stop
condition [P] (see
A device generating a message is a ‘transmitter’, a device receiving a message is the
‘receiver’. The device that controls the message is the ‘master’ and the devices which are
controlled by the master are the ‘slaves’.
Fig 13. Bit transfer
Fig 14. Definition of start and stop condition
2
C-bus is for bidirectional, two-line communication between different ICs or modules.
SDA
SCL
START condition
SDA
SCL
Figure
S
Rev. 01 — 8 April 2008
14).
DD
2
2
C-bus speed f
C-bus
the oscillator output OSC is switched to a high-impedance
data valid
data line
stable;
Figure
SCL
13).
allowed
change
of data
400 kHz, you must reduce the oscillator
Figure
8-bit A/D and D/A converter
STOP condition
5).
mbc621
P
PCA9691
© NXP B.V. 2008. All rights reserved.
mbc622
SDA
SCL
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