pca9691 NXP Semiconductors, pca9691 Datasheet - Page 19

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pca9691

Manufacturer Part Number
pca9691
Description
8-bit A/d And D/a Converter
Manufacturer
NXP Semiconductors
Datasheet

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NXP Semiconductors
PCA9691_1
Product data sheet
Fig 22. I
PROTOCOL
SDA
SCL
Rise and fall times refer to 30 % and 70 %
2
C-bus timing diagram
t
SU;STA
t
BUF
CONDITION
START
(S)
t HD;STA
Table 8.
V
C
[1]
[2]
Symbol Parameter
Analog output
V
I
Accuracy
E
E
E
t
f
LO
s(DAC)
c(DAC)
DD
L
AOUT
G
O
L
sup(n)
= 50 pF; unless otherwise specified.
= 5.0 V; V
The linearity error is assured if the internal frequency is changed by setting bit 7 and bit 3 of the control byte
to logic 1 (see
The time from the start of AOUT to a change of
t
LOW
voltage on pin AOUT
output leakage current
gain error
offset error
linearity error
DAC settling time
DAC conversion frequency
noise suppression
r t
D/A characteristics
BIT 7
MSB
SS
(A7)
t HIGH
= 0 V; V
Figure
5).
VREF
t SU;DAT
Rev. 01 — 8 April 2008
t
f
1 / f SCL
= 5.0 V; V
BIT 6
(A6)
t
HD;DAT
Conditions
no resistive load
R
pin AOUT disabled
no resistive load
f
f
f = 100 Hz;
V
SCL
SCL
AGND
n(VDD)(p-p)
L
= 10 k
> 400 kHz
= 0 V; T
400 kHz
1
2
LSB full scale (see
= 100 mV
(R/W)
BIT 0
LSB
amb
t VD;DAT
= 40 C to +85 C; R
ACKNOWLEDGE
[1]
[1]
[2]
(A)
Min
V
V
-
-
-
-
-
-
-
8-bit A/D and D/A converter
Section
100
SS
SS
7.3).
Typ
-
-
-
-
-
-
-
-
-
40
PCA9691
© NXP B.V. 2008. All rights reserved.
CONDITION
L
= 10 k ;
Max
V
0.9V
+100
1
2.4
44
-
STOP
(P)
20
1.0
1.5
DD
t SU;STO
DD
mbd820
19 of 28
Unit
V
V
nA
%
mV
LSB
LSB
kHz
dB
s

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