adv7174 Analog Devices, Inc., adv7174 Datasheet - Page 25

• Manufacturer Part Number: adv7174
• Description: Chip Scale Pal/ntsc Video Encoder With Advanced Power Management
• Manufacturer: Analog Devices, Inc.

POWER-ON RESET
After power-up, it is necessary to execute a reset operation. A
reset occurs on the falling edge of a high-to-low transition on
the RESET pin. This initializes the pixel port so that the pixel
inputs, P7–P0, are selected. After reset, the ADV7174/ADV7179
is automatically set up to operate in NTSC mode. Subcarrier
frequency code 21F07C16H is loaded into the subcarrier
frequency registers. All other registers, with the exception of
Mode Register 0, are set to 00H. With the exception of Bit MR44,
all bits in Mode Register 0 are set to Logic 0. Bit MR44 of Mode
Register 4 is set to Logic 1. This enables the 7.5 IRE pedestal.
SCH PHASE MODE
The SCH phase is configured in default mode to reset every
four (NTSC) or eight (PAL) fields to avoid an accumulation of
SCH phase error over time. In an ideal system, 0 SCH phase
error would be maintained forever, but in reality, this is impossi-
ble to achieve due to clock frequency variations. This effect is
reduced by the use of a 32-bit DDS, which generates this SCH.
Resetting the SCH phase every four or eight fields avoids the
accumulation of SCH phase error and results in very minor
SCH phase jumps at the start of the 4- or 8-field sequence.
Resetting the SCH phase should not be done if the video source
does not have stable timing or the ADV7174/ADV7179 is
configured in RTC mode (MR21 = 1 and MR22 = 1). Under
these conditions (unstable video), the subcarrier phase reset
should be enabled (MR22 = 0 and MR21 = 1), but no reset
applied. In this configuration, the SCH phase can never be reset,
which means that the output video can now track the unstable
input video. The subcarrier phase reset, when applied, resets the
SCH phase to Field 0 at the start of the next field, for example,
subcarrier phase reset applied in Field 5 (PAL) on the start of
the next field SCH phase is reset to Field 0.
MPU PORT DESCRIPTION
The ADV7174/ADV7179 supports a 2-wire serial (I
compatible) microprocessor bus driving multiple peripherals.
Two inputs, serial data (SDATA) and serial clock (SCLOCK),
carry information between any device connected to the bus.
Each slave device is recognized by a unique address. The
ADV7174/ADV7179 has four possible slave addresses for both
read and write operations. These are unique addresses for each
device and are illustrated in Figure 33 and Figure 34. The LSB
sets either a read or write operation. Logic 1 corresponds to a
read operation, while Logic 0 corresponds to a write operation.
A 1 is set by setting the ALSB pin of the ADV7174/ ADV7179 to
Logic 0 or Logic 1.
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To control the various devices on the bus, the following protocol
must be followed: first, the master initiates a data transfer by
establishing a start condition, defined by a high-to-low transition
on SDATA while SCLOCK remains high. This indicates that an
address/data stream will follow. All peripherals respond to the
start condition and shift the next eight bits (7-bit address + R/ W
bit). The bits transfer from MSB down to LSB. The peripheral
that recognizes the transmitted address responds by pulling the
data line low during the ninth clock pulse. This is known as an
Acknowledge bit. All other devices withdraw from the bus at
this point and maintain an idle condition. The idle condition is
where the device monitors the SDATA and SCLOCK lines wait-
ing for the start condition and the correct transmitted address.
The R/ W bit determines the direction of the data. A Logic 0 on
the LSB of the first byte means that the master will write infor-
mation to the peripheral. A Logic 1 on the LSB of the first byte
means that the master will read information from the peripheral.
The ADV7174/ADV7179 acts as a standard slave device on the
bus. The data on the SDATA pin is eight bits long, supporting
the 7-bit addresses plus the R/ W bit. The ADV7174/ADV7179
has 26 subaddresses to enable access to the internal registers. It
therefore interprets the first byte as the device address and the
second byte as the starting subaddress. The subaddresses’ auto
increment allows data to be written to or read from the starting
subaddress. A data transfer is always terminated by a stop
condition. The user can also access any unique subaddress
register on a one-by-one basis without having to update all the
registers. There is one exception. The subcarrier frequency
registers should be updated in sequence, starting with
Subcarrier Frequency Register 0. The auto increment function
should then be used to increment and access Subcarrier
Frequency Registers 1, 2, and 3. The subcarrier frequency
registers should not be accessed independently.
1
0
1
1
0
0
Figure 33. ADV7174 Slave Address
Figure 34. ADV7179 Slave Address
1
1
0
0
ADV7174/ADV7179
1
1
SET UP BY
SET UP BY
ADDRESS
CONTROL
ADDRESS
CONTROL
ALSB
ALSB
A1
A1
READ/WRITE
READ/WRITE
0
1
0
1
CONTROL
CONTROL
X
X
WRITE
READ
WRITE
READ