adv7174 Analog Devices, Inc., adv7174 Datasheet - Page 39

• Manufacturer Part Number: adv7174
• Description: Chip Scale Pal/ntsc Video Encoder With Advanced Power Management
• Manufacturer: Analog Devices, Inc.

APPENDIX 1—BOARD DESIGN AND LAYOUT CONSIDERATIONS
The ADV7174/ADV7179 is a highly integrated circuit contain-
ing both precision analog and high speed digital circuitry. It has
been designed to minimize interference effects on the integrity
of the analog circuitry by the high speed digital circuitry. It is
imperative that these same design and layout techniques be
applied to the system-level design so that high speed, accurate
performance is achieved. Figure 54 shows the analog interface
between the device and monitor.
The layout should be optimized for lowest noise on the
ADV7174/ADV7179 power and ground lines by shielding the
digital inputs and providing good decoupling. The lead length
between groups of V
reduce inductive ringing.
GROUND PLANES
The ground plane should encompass all ADV7174/ADV7179
ground pins, voltage reference circuitry, power supply bypass
circuitry for the ADV7174/ADV7179, the analog output traces,
and all the digital signal traces leading up to the ADV7174/
ADV7179. The ground plane is the board’s common ground
plane.
RESET
TELETEXT PULL-UP AND
PULL-DOWN RESISTORS
SHOULD ONLY BE USED
IF THESE PINS ARE NOT
CONNECTED
TTX
TTXREQ
3.3 V (V
3.3 V (V
(SAME CLOCK AS USED BY
4k :
100k :
100k :
100nF
CC
AA
)
)
MPEG2 DECODER)
AA
27MHz CLOCK
and GND pins should be minimized to
UNUSED
INPUTS
SHOULD BE
GROUNDED
3.3V (V
0.1 P F
AA
)
3.3 V (V
3.3 V (V
3–5, 35–39
10k :
0.1 P F
AA
AA
)
)
23
30
32
13
14
15
20
34
33
1
Figure 54. Recommended Analog Circuit Layout
P7–P0
BLANK
RESET
TTX
TTXREQ
CLOCK
COMP
V
SCRESET/RTC
HSYNC
FIELD/VSYNC
REF
ADV7174/ADV7179
ALSB
16
Rev. A | Page 39 of 52
V
POWER SUPPLY DECOUPLING
FOR EACH POWER SUPPLY GROUP
AA
GND
SCLOCK
DAC A
SDATA
DAC C
DAC B
R
0.1 P F
SET
POWER PLANES
The ADV7174/ADV7179 and any associated analog circuitry
should have its own power plane, referred to as the analog
power plane (V
the regular PCB power plane (V
ferrite bead. This bead should be located within 3 inches of the
ADV7174/ADV7179.
The metallization gap separating the device power plane and
board power plane should be as narrow as possible to minimize
the obstruction to the flow of heat from the device into the
general board.
The PCB power plane should provide power to all digital logic
on the PC board, and the analog power plane should provide
power to all ADV7174/ADV7179 power pins and voltage
reference circuitry.
Plane-to-plane noise coupling can be reduced by ensuring that
portions of the regular PCB power and ground planes do not
overlay portions of the analog power plane unless they can be
arranged so that the plane-to-plane noise is common mode.
24
28
29
21
22
31
0.01 P F
150 :
75 :
75 :
75 :
100 :
100 :
AA
3.3 V (V
). This power plane should be connected to
3.3 V (V
AA
10 P F
)
5k :
CC
)
(FERRITE BEAD)
3.3 V (V
CC
) at a single point through a
L1
5k :
ADV7174/ADV7179
CC
)
MPU BUS
33 P F
3.3 V
(V
GND
CC
)