adsp-21367kbpz-2a Analog Devices, Inc., adsp-21367kbpz-2a Datasheet - Page 14

• Manufacturer Part Number: adsp-21367kbpz-2a
• Description: Sharc Processors
• Manufacturer: Analog Devices, Inc.

ADSP-21367/ADSP-21368/ADSP-21369
Table 5. Pin List
1
2
The pull-up is always enabled on the ADSP-21367 and ADSP-21369 processors. The pull-up on the ADSP-21368 processor is only enabled on the processor with ID
Pull-up can be enabled/disabled, value of pull-up cannot be programmed.
Name
RESET
XTAL
CLKIN
RESETOUT/
CLKOUT
BR
ID
RPBA
2–0
4–1
Type
I
O
I
O/T
I/O (pu)
I (pd)
I (pu)
1
1
State During/
After Reset
(ID = 00x)
Driven low/
driven high
Pulled high/
pulled high
Rev. A | Page 14 of 56 | August 2006
Description
Processor Reset. Resets the processor to a known state. Upon deassertion, there is a
4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins program
execution from the hardware reset vector address. The RESET input must be asserted
(low) at power-up.
Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external
crystal.
Local Clock In. Used with XTAL. CLKIN is the processor’s clock input. It configures the
processors to use either its internal clock generator or an external clock source. Con-
necting the necessary components to CLKIN and XTAL enables the internal clock
generator. Connecting the external clock to CLKIN while leaving XTAL unconnected
configures the processor to use an external clock such as an external clock oscillator.
CLKIN may not be halted, changed, or operated below the specified frequency.
Reset Out/Local Clock Out. Reset out provide a 4096 cycle delay that allows the PLL
to lock. This pin can also be configured as a CLKOUT signal to clock synchronous periph-
erals and memory. The functionality can be switched between the PLL output clock and
reset out by setting Bit 12 of the PMCTL register. The default is reset out.
External Bus Request. Used by the ADSP-21368 processor to arbitrate for bus master-
ship. A processor only drives its own BR
inputs) and monitors all others. In a system with less than four processors, the unused
BR
because it is an output.
Processor ID. Determines which bus request (BR
cessor. ID = 001 corresponds to BR
ID = 000 or 001 in single-processor systems. These lines are a system configuration
selection that should be hardwired or only changed at reset. ID = 101,110, and 111 are
reserved.
Rotating Priority Bus Arbitration Select. When RPBA is high, rotating priority for the
ADSP-21368 external bus arbitration is selected. When RPBA is low, fixed priority is
selected. This signal is a system configuration selection which must be set to the same
value on every processor in the system.
x
pins should be tied high; the processor’s own BR
1,
ID = 010 corresponds to BR
x
line (corresponding to the value of its ID2-0
4–1
) is used by the ADSP-21368 pro-
x
line must not be tied high or low
2
, and so on. Use
2–0
= 00x