adsp-21367kbpz-2a Analog Devices, Inc., adsp-21367kbpz-2a Datasheet - Page 22

• Manufacturer Part Number: adsp-21367kbpz-2a
• Description: Sharc Processors
• Manufacturer: Analog Devices, Inc.

ADSP-21367/ADSP-21368/ADSP-21369
Clock Input
Table 14. Clock Input
1
2
3
4
5
Clock Signals
The processors can use an external clock or a crystal. See the
CLKIN pin description in
processor to use its internal clock generator by connecting the
necessary components to CLKIN and XTAL.
component connections used for a crystal operating in funda-
mental mode. Note that the clock rate is achieved using a
20.81 MHz crystal and a PLL multiplier ratio 16:1
(CCLK:CLKIN achieves a clock speed of 333 MHz). To achieve
the full core clock rate, programs need to configure the multi-
plier bits in the PMCTL register.
Parameter
Timing Requirements
t
t
t
t
t
t
Applies only for CLK_CFG1–0 = 00 and default values for PLL control bits in PMCTL.
Applies only for CLK_CFG1–0 = 10 and default values for PLL control bits in PMCTL.
Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t
Actual input jitter should be combined with ac specifications for accurate timing analysis.
Jitter specification is maximum peak-to-peak time interval error (TIE) jitter.
CK
CKL
CKH
CKRF
CCLK
CKJ
R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL DRIVE POWER.
REFER TO CRYSTAL MANUFACTURER’S SPECIFICATIONS
CLKIN
4, 5
3
C1
22pF
Figure 7. 333 MHz Operation (Fundamental Mode Crystal)
CLKIN
1M
24.576MHz
CLKIN Period
CLKIN Width Low
CLKIN Width High
CLKIN Rise/Fall (0.4 V to 2.0 V)
CCLK Period
CLKIN Jitter Tolerance
(TYPICAL)
Y1
R1
Figure 6. Clock Input
t
ADSP-2136x
CKH
Table
XTAL
5. Programs can configure the
C2
22pF
47
t
CK
(TYPICAL)
t
R2
CKL
Figure 7
Rev. A | Page 22 of 56 | August 2006
shows the
Min
18
8
8
3.0
–250
1
1
1
1
CCLK
.
333 MHz
Max
100
45
45
3
10
+250
2
2
2
Unit
ns
ns
ns
ns
ns
ps