adsp-21367kbpz-2a Analog Devices, Inc., adsp-21367kbpz-2a Datasheet - Page 30

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adsp-21367kbpz-2a

Manufacturer Part Number
adsp-21367kbpz-2a
Description
Sharc Processors
Manufacturer
Analog Devices, Inc.
Datasheet
ADSP-21367/ADSP-21368/ADSP-21369
Memory Read—Bus Master
Use these specifications for asynchronous interfacing to memo-
ries. These specifications apply when the processors are the bus
master accessing external memory space in asynchronous access
mode. Note that timing for ACK, DATA, RD, WR, and strobe
timing parameters only apply to asynchronous access mode.
Table 25. Memory Read—Bus Master
1
2
3
4
5
Parameter
Timing Requirements
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
W = (number of wait states specified in AMICTLx register) × t
HI =RHC + IC (RHC = number of read hold cycles specified in AMICTLx register) × t
IC = (number of idle cycles specified in AMICTLx register) × t
H = (number of hold cycles specified in AMICTLx register) × t
Data delay/setup: system must meet t
The falling edge of MSx is referenced.
Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only apply to asynchronous access mode.
Data hold: User must meet t
ACK Delay/Setup: User must meet t
DAD
DRLD
SDS
HDRH
DAAK
DSAK
DRHA
DARL
RW
RWR
ADDRESS
MSx
DATA
ACK
WR
RD
Address, Selects Delay to Data Valid
RD Low to Data Valid
Data Setup to RD High
Data Hold from RD High
ACK Delay from Address, Selects
ACK Delay from RD Low
Address Selects Hold After RD High
Address Selects to RD Low
RD Pulse Width
RD High to WR, RD Low
HDA
or t
HDRH
DAAK
DAD
, t
, or t
in asynchronous access mode. See
DRLD
t
DARL
DSAK
1
t
, or t
DAAK
4
, for deassertion of ACK (low). For asynchronous assertion of ACK (high) user must meet t
3, 4
SDS.
2
2, 5
t
Figure 18. Memory Read—Bus Master
DSAK
t
Rev. A | Page 30 of 56 | August 2006
DAD
1, 2
t
DRLD
SDCLK
SDCLK
SDCLK
Test Conditions on Page 47
.
.
.
Min
2.2
0
RH + 0.38
t
W – 1.2
HI +t
SDCLK
t
RW
SDCLK
–3.3
– 0.8
SDCLK
for the calculation of hold times given capacitive and dc loads.
t
SDS
Max
W+t
W– 2.9
t
W – 7.0
SDCLK
SDCLK
–9.5+ W
–5.12
t
t
HDRH
DRHA
t
RWR
DAAK
or t
DSAK
.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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