adsp-21469 Analog Devices, Inc., adsp-21469 Datasheet - Page 20

• Manufacturer Part Number: adsp-21469
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21469/ADSP-21469W
Table 12. Clock Periods
1
Timing
Requirements
t
t
t
t
t
t
t
where:
SR = serial port-to-core clock ratio (wide range, determined by SPORT CLKDIV
CK
CCLK
LCLK
PCLK
SCLK
DDR2_CLK
SPICLK
bits in DIVx register)
SPIR = SPI-to-Core Clock Ratio (wide range, determined by SPIBAUD register
setting)
SDR=DDR2 DRAM-to-Core Clock Ratio (Values determined by bits 20-18 of
the PMCTL register)
Description
CLKIN Clock Period
(Processor) Core Clock Period
(Link Port) Core Clock Period
(Peripheral) Clock Period = 2 × t
Serial Port Clock Period = (t
DDR2 DRAM Clock Period = (t
SPI Clock Period = (t
1
PCLLK
) × SPIR
Rev. PrB | Page 20 of 56 | November 2008
PCLK
CCLK
) × SR
CCLK
) × SDR
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
reflect statistical variations and worst cases. Consequently, it is
not meaningful to add parameters to derive longer times. See
Figure 41 on Page 50
ence levels.
Switching Characteristics specify how the processor changes its
signals. Circuitry external to the processor must be designed for
compatibility with these signal characteristics. Switching char-
acteristics describe what the processor will do in a given
circumstance. Use switching characteristics to ensure that any
timing requirement of a device connected to the processor (such
as memory) is satisfied.
Timing Requirements apply to signals that are controlled by cir-
cuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.
Preliminary Technical Data
under Test Conditions for voltage refer-