adsp-21469 Analog Devices, Inc., adsp-21469 Datasheet - Page 42

• Manufacturer Part Number: adsp-21469
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21469/ADSP-21469W
S/PDIF Transmitter
Serial data input to the S/PDIF transmitter can be formatted as
left justified, I
20-, or 24-bits. The following sections provide timing for the
transmitter.
S/PDIF Transmitter-Serial Input Waveforms
Figure 29
left channel and low for the right channel. Data is valid on the
rising edge of SCLK. The MSB is delayed 12-bit clock periods
(in 20-bit output mode) or 16-bit clock periods (in 16-bit output
Figure 30
for the left channel and HI for the right channel. Data is valid on
the rising edge of SCLK. The MSB is left-justified to an LRCLK
transition but with a single SCLK period delay.
Figure 31
left channel and LO for the right channel. Data is valid on the
rising edge of SCLK. The MSB is left-justified to an LRCLK
transition with no MSB delay.
DAI_P20-1
DAI_P20-1
DAI_P20-1
DAI_P20-1
DAI_P20-1
DAI_P20-1
DAI_P20-1
DAI_P20-1
DAI_P20-1
LRCLK
SDATA
LRCLK
SDATA
LRCLK
SDATA
SCLK
SCLK
SCLK
shows the right-justified mode. LRCLK is high for the
shows the default I
shows the left-justified mode. LRCLK is high for the
2
S, or right justified with word widths of 16-, 18-,
LSB
MSB
MSB-1
MSB
MSB-1
MSB-2
2
S-justified mode. LRCLK is low
MSB-2
MSB
LS B+2
LEFT CHANNEL
LEFT CHANNEL
MSB-1
LSB+2 LSB+1
LSB+1
LEFT CHANNEL
MSB-2
Rev. PrB | Page 42 of 56 | November 2008
LSB
Figure 29. Right-Justified Mode
Figure 31. Left-Justified Mode
LSB
Figure 30. I
LSB+2 LSB+1
2
S-Justified Mode
LSB
MSB
mode) from an LRCLK transition, so that when there are 64
SCLK periods per LRCLK period, the LSB of the data will be
right-justified to the next LRCLK transition.
RIGHT CHANNEL
MSB-1
MSB
MSB-2
MSB-1
MSB-2
RIGHT CHANNEL
Preliminary Technical Data
RIGHT CHANNEL
LSB+2
MSB
MSB-1
LSB +1
LSB+2
MSB-2
LSB+1
LSB
LSB
LSB+2
LSB+1
MSB
LSB
MSB+1
MSB