adsp-21469 Analog Devices, Inc., adsp-21469 Datasheet - Page 31

• Manufacturer Part Number: adsp-21469
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
Memory Write—Bus Master
Use these specifications for asynchronous interfacing to memo-
ries. Note that timing for AMI_ACK, AMI_DATA, AMI_RD,
AMI_WR, and strobe timing parameters only apply to asyn-
chronous access mode.
Table 27. Memory Write—Bus Master
1
2
3
4
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
t
t
t
t
t
t
W = (number of wait states specified in AMICTLx register) × t
AMI_ACK delay/setup: System must meet t
The falling edge of AMI_MSx is referenced.
Note that timing for AMI_ACK, AMI_DATA, AMI_RD, AMI_WR, and strobe timing parameters only applies to asynchronous access mode.
See
DAAK
DSAK
DAWH
DAWL
WW
DDWH
DWHA
DWHD
DATRWH
WWR
DDWR
WDE
Test Conditions on Page 50
AMI_ADDR
AMI_DATA
AMI_WR
AMI_ACK
MSx
AMI_RD
AMI_ACK Delay from Address, Selects
AMI_ACK Delay from AMI_WR Low
Address, Selects to AMI_WR Deasserted
Address, Selects to AMI_WR Low
AMI_WR Pulse Width
Data Setup Before AMI_WR High
Address Hold After AMI_WR Deasserted
Data Hold After AMI_WR Deasserted
Data Disable After AMI_WR Deasserted
AMI_WR High to AMI_WR, AMI_RD Low
Data Disable Before AMI_RD Low
AMI_WR Low to Data Enabled
for calculation of hold times given capacitive and dc loads.
DAAK
t
t
DAWL
DAAK
, or t
t
WDE
DSAK
, for deassertion of AMI_ACK (low). For asynchronous assertion of AMI_ACK (high) user must meet t
Rev. PrB | Page 31 of 56 | November 2008
Figure 19. Memory Write—Bus Master
2
t
DSAK
1, 3
1, 2
4
2
S
DDR2_CLK
t
DAWH
Min
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
H = (number of hold cycles specified in AMICTLx register) x t
t
WW
t
DDWH
ADSP-21469/ADSP-21469W
Max
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
t
DATRWH
t
DWHD
t
t
t
DWHA
WWR
DDWR
DAAK
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DDR2_CLK
or t
DSAK
.