adsp-21469 Analog Devices, Inc., adsp-21469 Datasheet - Page 32

• Manufacturer Part Number: adsp-21469
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21469/ADSP-21469W
Link Ports
Calculation of link receiver data setup and hold relative to link
clock is required to determine the maximum allowable skew
that can be introduced in the transmission path between
LDATA and LCLK. Setup skew is the maximum delay that can
be introduced in LDATA relative to LCLK, (setup skew = t
TWH
that can be introduced in LCLK relative to LDATA, (hold skew
= t
Table 28. Link Ports – Receive
1
Parameter
Timing Requirements
t
t
t
t
t
Switching Characteristics
t
LACK goes low with tDLALC relative to rise of LCLK after first byte, but does not go low if the receiver's link buffer is not about to fill.
SLDCL
HLDCL
LCLKIW
LCLKRWL
LCLKRWH
DLALC
LCLKTWL
min– t
DLDCH
min – t
LDAT7-0
LACK (OUT)
LCLK
Data Setup Before LCLK Low
Data Hold After LCLK Low
LCLK Period
LCLK Width Low
LCLK Width High
LACK Low Delay After LCLK High
– t
HLDCH
SLDCL
– t
). Hold skew is the maximum delay
HLDCL
). Calculations made directly
t
LCLKRWH
Rev. PrB | Page 32 of 56 | November 2008
1
t
Figure 20. Link Ports—Receive
SLDCL
IN
LCLK-
t
LCLKIW
t
HLDCL
from speed specifications will result in unrealistically small skew
times because they include multiple tester guardbands. The
setup and hold skew times shown below are calculated to
include only one tester guardband.
ADSP-21469 Setup Skew = TBD ns max
ADSP-21469 Hold Skew = TBD ns max
Note that there is a two-cycle effect latency between the link
port enable instruction and the DSP enabling the link port.
t
LCLKRWL
Min
TBD
TBD
TBD
TBD
TBD
TBD
TBD
t
DLALC
Preliminary Technical Data
Max
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Unit
ns
ns
ns
ns
ns
ns