saa7712h NXP Semiconductors, saa7712h Datasheet - Page 16

• Manufacturer Part Number: saa7712h
• Description: Sound Effects Dsp
• Manufacturer: NXP Semiconductors

Philips Semiconductors
8.2.2
The SAA7712H has two slave I
I
I
I
I
the bit clock and word select. The I
audio_format(2 to 0) allow for selection of the desired
I
selecting a certain format, are explained in Table 2.
The input circuitry is limited in handling the number of BCK
pulses per WS period. If the word rate of the selected
digital input source is f
clock in the range of 16f
limit of the audio sample frequency is determined by
1
is determined by DSP_clock/481 Hz.
Table 2 I
The selection of the DSP input among the decimated
analog input and the I
is controlled with I
The meaning of this bit can be found in Table 3.
1999 Aug 05
2
2
2
2
2
18
BIT 9
S_IN2 with respective data lines I
S_IN2_DATA, word select lines I
S_IN2_WS and bit clock lines I
S_IN2_BCK. The external source is master and supplies
S-bus format (see Table 13). The bits, needed for
Sound effects DSP
f
0
1
AUDIO_FORMAT
SCL
. The maximum limit of the audio sample frequency
S
see Table 13)
BIT 8
LAVE
2
C-bus audio_format mode bits (0FF9H,
0
0
1
1
0
I
2
S-
2
BIT 7
C-bus bit audio_source (see Table 13).
BUS INPUTS
0
1
0
1
0
2
s
S-bus inputs I
, the bit clock must be a continuous
s
internal format (for test
purposes only)
LSB-justified, 16 bits
LSB-justified, 18 bits
LSB-justified, 20 bits
standard I
f
bit(CLK)
2
S-bus inputs, I
2
S_IN1_BCK and
2
2
2
S_IN1_WS and
C-bus bits
S_IN1_DATA and
2
2
256f
OUTPUT
S-bus (default)
S_IN1 and I
s
. The minimum
2
S_IN1 and
2
S_IN2
16
Table 3 I
8.2.3
For the co-processor I/O interface, the SAA7712H acts as
a master. The SAA7712H supplies both the bit clock and
word select. The I
allow for selection of the desired I
Table 13).
The bits needed for selecting a certain format are given in
Table 4.
All I
I
I
The word select and bit clock of the co-processor I/O
interface are derived from the word select and bit clock of
the audio source selected according to Table 3.
The incoming bit clock can be divided by 1, 2, 4 or 8
depending on the needs of an external connected
co-processor. These selections can be done with I
bits cloop_mode(2 to 0) (see Table 13). The meaning of
these bits is shown in Table 5.
2
2
S_IO_OUT1 and I
C-bus bit en_host_io (see Table 13).
2
S-bus output lines, I
AUDIO_SOURCE
M
see Table 13)
2
ASTER
C-bus audio_source mode bit (0FF9H,
Bit 5
0
1
I
2
2
C-bus bits host_io_format(1 and 0)
S-
2
S_IO_OUT2, can be 3-stated with
BUS INPUTS AND OUTPUTS
2
S_IO_WS, I
I
I
2
2
S_IN1 (default)
S_IN2
Preliminary specification
2
S-bus format (see
2
SAA7712H
S_IO_BCK,
OUTPUT
2
C-bus