saa7712h NXP Semiconductors, saa7712h Datasheet - Page 21

• Manufacturer Part Number: saa7712h
• Description: Sound Effects Dsp
• Manufacturer: NXP Semiconductors

Philips Semiconductors
8.6
8.6.1
A general description of the I
obtained from Philips Semiconductors, International
Marketing and Sales Communications (IMSC).
For the external control of the SAA7712H a fast I
is implemented. This is a 400 kHz bus which is downward
compatible with the standard 100 kHz bus.
There are different types of control instructions:
The detailed description of the I
given in the following sections. The description of the
different bits in the memory map is given in Section 9.6.
The equalizer cannot be used and cannot be
programmed if there is no word select and bit clock signal
present on a selected digital source input; see
audio_source bit in Table 3 (I
The minimum limit of the audio sample frequency is
determined by
1999 Aug 05
handbook, full pagewidth
Instructions to control the DSP program, program the
coefficient RAM and read the values of parameters
Instructions to control the equalizer, program the
equalizer coefficient RAM to be able to change the
centre frequency, gain and Q-factor of the equalizer
sections
Instructions to control the source selection and
programmable parts, e.g. PLL clock speed.
Sound effects DSP
I
2
C-bus control
I
NTRODUCTION
1
18
f
SCL
.
SDA
SCL
2
2
C-bus format can be
S_IN1 and I
2
C-bus and commands is
Fig.11 Bit transfer on the I
2
S_IN2).
data valid
data line
stable;
2
C-bus
allowed
change
of data
21
8.6.2
The I
different ICs or modules. The two lines are a serial data
line (SDA) and a serial clock line (SCL). Both lines must
be connected to V
connected to the output stages of a microcontroller. For a
400 kHz I
Semiconductors must be followed (e.g. up to loads of
200 pF on the bus a pull-up resistor can be used, between
200 to 400 pF a current source or switched resistor must
be used). Data transfer can only be initiated when the bus
is not busy.
8.6.3
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable during the
HIGH period of the clock pulse as changes in the data line
at this time will be interpreted as control signals
(see Fig.11). The maximum clock frequency is 400 kHz.
To be able to run on this high frequency all the inputs and
outputs connected to this bus must be designed for this
high speed I
2
C-bus is for 2-way, 2-line communication between
2
C-bus.
C
B
2
C-bus the recommendation from Philips
IT TRANSFER
HARACTERISTICS OF THE
2
C-bus according to the Philips specification.
DD
MGS216
via a pull-up resistor when
Preliminary specification
I
2
C-
SAA7712H
BUS