saa7712h NXP Semiconductors, saa7712h Datasheet - Page 20

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saa7712h

Manufacturer Part Number
saa7712h
Description
Sound Effects Dsp
Manufacturer
NXP Semiconductors
Datasheet

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8.5
The clock of the DSP is generated with a programmable PLL.
To select the required DSP clock see Table 6. The N factor (ranging from 93 to 181) can be selected with I
PLL_div(14 to 11), see Table 10. Depending on the crystal and the required DSP clock the I
bits dsp_turbo must be set. The maximum limit of the audio sample frequency is determined by DSP_clock/481 Hz.
Table 6 I
Notes
1. f
2. f
3. Usable frequency.
1999 Aug 05
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Sound effects DSP
xtal
xtal
PLL_DIV(14 to 11)
Programmable phase-locked loop circuit
= 16.384 MHz; pll_fs_sel = 1 and dsp_turbo = 1, see Table 11.
= 18.432 MHz; pll_fs_sel = 1 and dsp_turbo = 1, see Table 11.
2
C-bus bits PLL_div and dividing factors N of the programmable DSP clock
93 (default)
106
113
121
126
132
137
143
148
154
159
165
170
176
181
99
N
20
TDA9875
23.808
25.344
33.792
35.072
36.608
37.888
39.424
40.704
42.240
43.520
45.056
46.336
27.136
28.928
30.976
32.256
DSP CLOCK FREQUENCY (MHz)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(1)
2
C-bus bits pll_fs_sel and
Preliminary specification
MSP3410D
SAA7712H
34.848
36.288
38.016
39.456
41.184
42.624
44.352
45.792
47.520
48.960
50.688
52.128
26.784
28.512
30.528
32.544
2
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
C-bus bits
(2)

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