saa7712h NXP Semiconductors, saa7712h Datasheet - Page 17

• Manufacturer Part Number: saa7712h
• Description: Sound Effects Dsp
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 4 I
Table 5 I
8.3
8.3.1
The equalizer accelerator is a hardware accelerator to the
DSP core. Both its inputs and outputs are stored in
registers of the DSP core.
The equalizer cannot be used and cannot be programmed
if no word select and bit clock signal are present on a
selected digital source input; see audio_source bit in
Table 3 (I
DSP_clock is 481f
The equalizer accelerator contains one second-order filter
data path that is 20 times multiplexed. With this circuit, a
2-channel equalizer of 10 second-order sections per
channel or a 4-channel equalizer of 5 second-order
sections per channel can be realised. The centre
frequency, gain and Q-factor of all 20 second-order
sections can be set independently from each other. Every
section is followed by a selectable attenuation of 0 or 6 dB.
Per section, 4 bytes of the I
store the settings. The equalizer settings can be updated
during normal operation. An application program supports
the programming of the equalizer.
1999 Aug 05
Sound effects DSP
Equalizer accelerator
BIT 15
I
2
NTRODUCTION
S_IN1 or I
2
2
0
1
C-bus host_io_format bits (0FF9H, see Table 13)
C-bus cloop_mode bits (0FF9H, see Table 13)
BIT 11
0
0
1
1
s
.
2
S_IN2). The minimum required
HOST_IO_FORMAT
CLOOP_MODE
2
C-bus register are needed to
BIT 14
0
0
1
1
BIT 10
0
1
0
1
BIT 13
0
1
0
1
17
If the gain setting causes the audio signal to exceed the
maximum level in one of the filter sections, the signal will
be clipped and the equalizer overflow output (pin EQOV)
will be set HIGH until the end of the next audio sample
period.
8.3.2
The equalizer accelerator can make a 2-channel equalizer
of 10 second-order sections per channel or a 4-channel
equalizer of 5 second-order sections per channel.
The sections of one channel can be chained one after the
other. Depending on the I
(see Table 11), the 20 filter sections are combined for the
appropriate configuration, as illustrated in Fig.8.
standard I
LSB-justified format, 16 bits
LSB-justified format, 18 bits
LSB-justified format, 20 bits
bypass WS (default)
WS 50% duty factor
bypass BCLK (default)
divide BCLK by 2
divide BCLK by 4
divide BCLK by 8
C
ONFIGURATION OF EQUALIZER SECTIONS
2
S-bus (default)
2
C-bus control bit two_four
OUTPUT
OUTPUT
Preliminary specification
SAA7712H