admcf340 Analog Devices, Inc., admcf340 Datasheet - Page 26

• Manufacturer Part Number: admcf340
• Description: Dashdsptm 64-lead Flash Mixed-signal Dsp With Enhanced Analog Front End
• Manufacturer: Analog Devices, Inc.

ADMCF340
Also SPORT1 Flag signal (FL1) is externally available through
the FL1/DT1 Pin. This signal is used to drive the external serial
memory input reset.
With SPORT1 configured in UART Mode, the SPORT0 serial
clock (SCLK0) is externally available through the SCLK1/
SCLK0 Pin. The SPORT1 data transmit (DT1) is externally
available through the FL1/DT1 Pin.
SPORT0 Configuration
SPORT0 can be configured in the following modes:
SPORT0 can be configured for UART Mode. In this mode,
the DR0 and RFS0 signals of the internal serial port are
connected together.
SPORT Mode
UART Mode
SPI Mode
Figure 18. SPORT0 and SPORT1 Internal Multiplexing (Simplied Diagram)
SPORT0 SPORT MODE/UART MODE
DSP
CORE
SPORT1
DSP
CORE
SPORT0
ADMCF340
MODECTRL REGISTER (15)
SCLK1
SCLK0
RFS1
RFS0
TFS1
TFS0
DR1
DR0
DT1
DT0
FL1
SPORT1 BOOT MODE/UART MODE
MODECTRL REGISTER (04)
SPORT0 SPI INTERFACE CONTROL
MODECTRL REGISTER (14..13..12)
–26–
SPORT0 can be configured to operate as master SPI interface.
The SPI Mode is set through Bit 14 of MODECTRL Register.
When SPORT0 is configured as SPI interface, the SPORT I/O
pins assume the configuration shown in Table XI.
The Slave Select Pin automatically generates the select signal at
each word transfer. This pin can also be used as a general purpose
I/O during the SPI transfer without affecting the SPORT operations.
The SPI clock polarity and phase are configurable through
Bits 13 and 12 of MODECTRL Register. The SPI transfer using
clock phase is shown in Figure 19 and Figure 20.
CONTROL
BLOCK
SPI
DT1/FL1
DR1
SCLK1/SCLK0
DT0
DR0
TFS0
RFS0
REV. 0