admcf340 Analog Devices, Inc., admcf340 Datasheet - Page 16

• Manufacturer Part Number: admcf340
• Description: Dashdsptm 64-lead Flash Mixed-signal Dsp With Enhanced Analog Front End
• Manufacturer: Analog Devices, Inc.

ADMCF340
In general, the on-times of the PWM signals in double update
mode are defined by:
T
T
because of the completely general case in double update mode,
the switching period is given by:
Again, the values of T
zero and T
16-BIT PWM TIMER
Parameter
Counter Resolution
Edge Resolution (Single Update Mode)
Edge Resolution (Double Update Mode)
Programmable Dead Time Range
Programmable Dead Time Increments
Programmable Pulse Deletion Range
Programmable Pulse Deletion Increments
PWM Frequency Range
PWMSYNC Pulsewidth (T
Gate Drive Chop Frequency Range
PWMDT
AH
AL
= (PWMTM
= (PWMCHA
d
d
1
AH
AL
S
– PWMDT
.
T
=
−
=
–
=
S
=
(
PWMCHA
PWMTM
(
PWMDT
PWMCHA
T
=
PWMTM
T
PWMTM
T
T
1
AL
(
AH
S
1
S
PWNMTM
+ PWMTM
+ PWMCHA
Table IV. Fundamental Characteristics of PWM Generation Unit of ADMCF340
AH
PWMTM
2
PWMTM
) × T
1
1
and T
1
1
1
+
+
2
+
+
+
PWMDT
PWMTM
CK
+
PWMTM
PWMCHA
PWMTM
CRST
2
PWMDT
1
AL
– PWMCHA
+
2
1
1
– PWMDT
+
are constrained to lie between
PWMTM
+
)
PWMTM
PWMTM
2
2
2
2
1
2
+
+
PWMCHA
PWMDT
1
1
2
)
– PWMDT
– PWMCHA
2
2
×
T
CK
2
)
1
)
2
) × T
2
–
CK
–16–
PWM signals similar to those illustrated in Figure 7 and Figure 8 can
be produced on the BH, BL, CH, and CL outputs by programming
the PWMCHB and PWMCHC Registers in a manner identical
to that described for PWMCHA.
The PWM controller does not produce any PWM outputs until
all of the PWMTM, PWMCHA, PWMCHB, and PWMCHC
Registers have been written to at least once. After these registers
have been written, the counters in the three-phase timing unit
are enabled. Writing to these registers also starts the main PWM
timer. If during initialization, the PWMTM Register is written
before the PWMCHA, PWMCHB, and PWMCHC Registers, the
first PWMSYNC pulse (and interrupt if enabled) will be generated
(1.5 × T
PWMTM Register in single update mode. In double update mode,
the first PWMSYNC pulse will be generated (T
seconds after the initial write to the PWMTM Register in single
update mode.
Effective PWM Resolution
In single update mode, the same values of PWMCHA, PWMCHB,
and PWMCHC are used to define the on-times in both half
cycles of the PWM period. As a result, the effective resolution of
the PWM generation process is 2 T
CLKOUT) since incrementing one of the duty cycle registers by
one changes the resultant on-time of the associated PWM signals
by T
In double update mode, improved resolution is possible since
different values of the duty cycle registers are used to define the
on-times in both the first and second halves of the PWM period.
As a result, it is possible to adjust the on-time over the whole
period in increments of T
PWM resolution of T
20 MHz CLKOUT).
CK
in each half period (or 2 T
CK
× PWMTM) seconds after the initial write to the
Min
0
153
0.05
0.02
CK
in double update mode (or 50 ns for a
Typ
16
100
50
100
0
50
CK
. This corresponds to an effective
CK
CK
for the full period).
(or 100 ns for a 20 MHz
Max
102
51
12.8
5
CK
× PWMTM)
Unit
Bits
ns
ns
µs
ns
µs
ns
Hz
µs
MHz
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