admcf340 Analog Devices, Inc., admcf340 Datasheet - Page 24

• Manufacturer Part Number: admcf340
• Description: Dashdsptm 64-lead Flash Mixed-signal Dsp With Enhanced Analog Front End
• Manufacturer: Analog Devices, Inc.

ADMCF340
Figure 17. Typical Auxiliary PWM Signals (All Times in
Increments of T
WATCHDOG TIMER
The ADMCF340 incorporates a watchdog timer that can perform
a full reset of the DSP and motor control peripherals in the event
of software error. The watchdog timer is enabled by writing a
timeout value to the 16-bit WDTIMER Register. The timeout
value represents the number of CLKIN cycles required for the
watchdog timer to count down to zero. When the watchdog timer
reaches zero, a full DSP core and motor control peripheral reset
is performed. In addition, Bit 1 of the SYSSTAT Register is set
so that after a watchdog reset, the ADMCF340 can determine
that the reset was due to the timeout of the watchdog timer
and not an external reset. Following a watchdog reset, Bit 1 of
the SYSSTAT Register may be cleared by writing zero to the
WDTIMER Register. This clears the status bit but does not
enable the watchdog timer.
On reset, the watchdog timer is disabled and is only enabled
when the first timeout value is written to the WDTIMER Register.
To prevent the watchdog timer from timing out, the user must write
to the WDTIMER Register at regular intervals (shorter than the
programmed WDTIMER period value). On all but the first write
to WDTIMER, the particular value written to the register is
unimportant, since writing to WDTIMER simply reloads the first
value written to this register.
PROGRAMMABLE DIGITAL INPUT/OUTPUT
The ADMCF340 has 25 programmable digital input/output
(PIO) pins. These pins are organized in two separate ports:
PORTA (nine pins) and PORTB (16 pins).
The nine pins of PORTA are multiplexed with other on-chip
peripheral functions. PORTB has 16 pins that are dedicated to
the digital I/O function only.
Each bit of PORTA can be individually selected as PIO or the
alternate function through PORTA_SELECT Register. Bit 0 of
PORTA_SELECT controls the operation of the PA0 Pin, Bit 1
controls the operation of PA1 and so on. Setting the appropriate
bit in the PORTA_SELECT Register causes the corresponding
pin to be configured as PIO. Clearing the bit selects the alternate
function of the corresponding pin. Following a power-on or reset,
all bits of PORTA_SELECT are set such that PIO functionality
is selected. The second alternate function of PA7 is selected by
Bit 14 of the PORTA_SELCT Register. The second alternate
function of PA8 is selected by Bit 15 of PORTA_SELECT
Register. The second alternate function of PA4 and PA5 is selected
by Bit 4 of MODECTRL Register (SPORT1 Mode: Boot/UART).
AUX0
AUX1
2
(AUXTM1 + 1)
2
AUXCH0
CK
)
(b) Offset Mode
2
AUXCH1
2
2
(AUXTM0 + 1)
(AUXTM0 + 1)
–24–
When a pin is operating as PIO, its direction can be set through
the corresponding bit of the data direction register (PORTA_DIR
or PORTB_DIR).
Clearing any bit of the data direction register configures the
corresponding PIO as input while setting the bit configures the
PIO as output.
Following a power-on or reset, all bits or PORTA_DIR and
PORTB_DIR are cleared, configuring all the PIO lines as inputs.
The data of the PIOs is controlled by the data registers
(PORTA_DATA and PORTB_DATA). These registers can be
used to read data from those PIOs configured as input and write
data to those configured as outputs.
Each PIO can be individually programmed to be an interrupt
source by setting the corresponding bit of the interrupt enable
register (PORTA_INTEN and PORTB_INTEN). To generate
an interrupt, the corresponding bit on the data register
(PORTA_DATA and PORTB_DATA) must change state
(high-to-low or low-to-high transition). The transition can be on
the corresponding pin (PIO configured as input) or by writing
into the corresponding bit of the data register (PIO configured as
output).
Following a change of state on the data register on a PIO
configured as interrupt source the corresponding bit is set in
the flag register (PORTA_FLAG and PORTB_FLAG) and a
common PIO interrupt is generated.
Reading the flag register is possible to determine which PIO has
generated the interrupt. Reading the flag register automatically
clears all the bits of the register. Following a power-on or reset,
all bits of the interrupt enable registers are cleared (no interrupt
enabled).
Each PIO line has an internal pull-down resistor so that following
a power-on or reset all the PIO lines will be read as logic lows
if left unconnected.
Once a pin has been selected as PIO function, it can be set as
input, output, and interrupt source (either configured as
input or output).
PIO Registers
The configuration of all registers of the PIO system is shown at
the end of the data sheet.
INTERRUPT CONTROL
The ADMCF340 can respond to 34 different interrupt sources
with minimal overhead. Seven of these interrupts are internal
DSP core interrupts and 27 are from the on-chip peripherals.
The seven DSP core interrupts are SPORT0 receive and trans-
mit, SPORT1 receive (or IRQ0 ) and transmit (or IRQ1), the
internal timer, and two software interrupts. The Motor Control
interrupts are the 25 PIOs and two from the PWM block
(PWMSYNC pulse and PWMTRIP). All the on-chip peripherals
interrupts are multiplexed into the DSP core via the peripheral
IRQ2 interrupt. They are also internally prioritized and individually
maskable. The start address in the interrupt vector table for the
ADMCF340 interrupt sources is shown in Table X. The interrupts
are listed from high priority to the lowest priority. The
PWMSYNC interrupt is triggered by a low-to-high transition on the
PWMSYNC pulse. The PWMTRIP interrupt is triggered on a high-
to-low transition on the PWMTRIP pin. A PIO interrupt is detected
on any change of state (high-to-low or low-to-high) on the PIO lines.
REV. 0